LP5024 datasheet(19/59 Pages) TI2

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to the bus. The two interface lines are the serial data line (SDA) and the serial clock line (SCL). Every device on

the bus is assigned a unique address and acts as either a master or a slave depending on whether it generates

or receives the serial clock, SCL. The SCL and SDA lines should each have a pullup resistor placed somewhere

on the line and remain HIGH even when the bus is idle.

7.5.1.1 Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state

of the data line can only be changed when the clock signal is LOW.

Figure 7-8. Data Validity

7.5.1.2 Start and Stop Conditions

START and STOP conditions classify the beginning and the end of the data transfer session. A START condition

is defined as the SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. A STOP condition

is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The bus master always generates

START and STOP conditions. The bus is considered to be busy after a START condition and free after a STOP

condition. During data transmission, the bus master can generate repeated START conditions. First START and

repeated START conditions are functionally equivalent.

Figure 7-9. Start and Stop Conditions

7.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most-significant bit (MSB) being transferred first.

Each byte of data must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated

by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The device

pulls down the SDA line during the ninth clock pulse, signifying an acknowledge. The device generates an

acknowledge after each byte has been received.

There is one exception to the acknowledge-after-every-byte rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not acknowledging (negative acknowledge) the last byte clocked out

of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),

but the SDA line is not pulled down.

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LP5018, LP5024

SLVSEB8C – OCTOBER 2018 – REVISED JULY 2024

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