 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
DM505 датащи(PDF) 91 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
DM505 датащи(HTML) 91 Page - Texas Instruments |
|
|
91 / 295 page  91 DM505 www.ti.com SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 Submit Documentation Feedback Specifications Copyright © 2016–2018, Texas Instruments Incorporated Table 5-6. LVCMOS DDR DC Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER MIN NOM MAX UNIT ZO Output impedance (drive strength) l[2:0] = 000 (Imp80) 80 Ω l[2:0] = 001 (Imp60) 60 l[2:0] = 010 (Imp48) 48 l[2:0] = 011 (Imp40) 40 l[2:0] = 100 (Imp34) 34 Single-Ended Receiver Mode VIH High-level input threshold DDR3/DDR3L VREF+0.1 VDDS+0.2 V VIL Low-level input threshold DDR3/DDR3L -0.2 VREF-0.1 V VCM Input common-mode voltage VREF -1%VDDS VREF+ 1%VDDS V CPAD Pad capacitance (including package capacitance) pF Signal Names in MUXMODE 0 (Differential Signals): ddr1_dqs[3:0], ddr1_dqsn[3:0], ddr1_ck, ddr1_nck, ddr1_dqs_ecc, ddr1_dqsn_ecc; Driver Mode VOH High-level output threshold (IOH = 0.1 mA) 0.9×VDDS V VOL Low-level output threshold (IOL = 0.1 mA) 0.1×VDDS V CPAD Pad capacitance (including package capacitance) 3 pF ZO Output impedance (drive strength) l[2:0] = 000 (Imp80) 80 Ω l[2:0] = 001 (Imp60) 60 l[2:0] = 010 (Imp48) 48 l[2:0] = 011 (Imp40) 40 l[2:0] = 100 (Imp34) 34 Single-Ended Receiver Mode VIH High-level input threshold DDR3/DDR3L VREF+0.1 VDDS+0.2 V VIL Low-level input threshold DDR3/DDR3L -0.2 VREF-0.1 V VCM Input common-mode voltage VREF -1%VDDS VREF+ 1%VDDS V CPAD Pad capacitance (including package capacitance) 3 pF Differential Receiver Mode VSWING Input voltage swing DDR3/DDR3L 0.4×vdds 0.6×vdds V VCM Input common-mode voltage VREF -1%VDDS VREF+ 1%VDDS V CPAD Pad capacitance (including package capacitance) 3 pF (1) VDDS in this table stands for corresponding power supply (i.e. vdds_ddr1 or vdds_ddr2). For more information on the power supply name and the corresponding ball, see Table 4-1, POWER [10] column. (2) For more information on the I/O cell configurations (i[2:0], sr[1:0]), see Control Module section of the Device TRM. Table 5-7. Dual Voltage LVCMOS I2C DC Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER MIN NOM MAX UNIT Signal Names in MUXMODE 0: i2c2_scl; i2c1_scl; i2c1_sda; i2c2_sda; |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
