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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DM505 датащи(PDF) 47 Page - Texas Instruments |
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DM505 датащи(HTML) 47 Page - Texas Instruments |
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47 / 295 page  47 DM505 www.ti.com SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 Submit Documentation Feedback Terminal Configuration and Functions Copyright © 2016–2018, Texas Instruments Incorporated Table 4-9. EMIF Signal Descriptions (continued) SIGNAL NAME DESCRIPTION TYPE BALL ddr1_d27 EMIF1 Data Bus IO U20 ddr1_d28 EMIF1 Data Bus IO R22 ddr1_d29 EMIF1 Data Bus IO V20 ddr1_d30 EMIF1 Data Bus IO W22 ddr1_d31 EMIF1 Data Bus IO U22 ddr1_ecc_d0 EMIF1 ECC Data Bus IO Y11 ddr1_ecc_d1 EMIF1 ECC Data Bus IO AA12 ddr1_ecc_d2 EMIF1 ECC Data Bus IO AA11 ddr1_ecc_d3 EMIF1 ECC Data Bus IO Y9 ddr1_ecc_d4 EMIF1 ECC Data Bus IO AA13 ddr1_ecc_d5 EMIF1 ECC Data Bus IO AB11 ddr1_ecc_d6 EMIF1 ECC Data Bus IO AA9 ddr1_ecc_d7 EMIF1 ECC Data Bus IO AB9 ddr1_dqm0 EMIF1 Data Mask IO AB8 ddr1_dqm1 EMIF1 Data Mask IO Y18 ddr1_dqm2 EMIF1 Data Mask IO AB3 ddr1_dqm3 EMIF1 Data Mask IO W21 ddr1_dqm_ecc EMIF1 ECC Data Mask IO AB13 ddr1_dqs0 Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO AA5 ddr1_dqs1 Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO AA20 ddr1_dqs2 Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO W1 ddr1_dqs3 Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO T21 ddr1_dqsn0 Data strobe 0 invert IO AB5 ddr1_dqsn1 Data strobe 1 invert IO Y20 ddr1_dqsn2 Data strobe 2 invert IO W2 ddr1_dqsn3 Data strobe 3 invert IO T22 ddr1_dqsn_ecc EMIF1 ECC Complementary Data strobe IO AB10 ddr1_dqs_ecc EMIF1 ECC Data strobe input/output. This signal is output to the EMIF1 memory when writing and input when reading. IO AA10 4.3.9 GPMC NOTE For more information, see the Memory Subsystem / General-Purpose Memory Controller section of the Device TRM. Table 4-10. GPMC Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BALL gpmc_ad0 GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1 in A/D multiplexed mode IO E8 gpmc_ad1 GPMC Data 1 in A/D nonmultiplexed mode and additionally Address 2 in A/D multiplexed mode IO A7 gpmc_ad2 GPMC Data 2 in A/D nonmultiplexed mode and additionally Address 3 in A/D multiplexed mode IO F8 gpmc_ad3 GPMC Data 3 in A/D nonmultiplexed mode and additionally Address 4 in A/D multiplexed mode IO B7 |
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