CC115LRGP datasheet(20/74 Pages) TI2

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Read or write consecutive

Write n + 1 bytes

registers (s):

to the TX FIFO:

HeaderStrobe

HeaderReg

HeaderReg n

HeaderFIFO

HeaderReg

Data

Datan

DataByte 0

Data

HeaderReg

Data

HeaderReg

Data

Datan + 1

Datan + 2

HeaderStrobe

HeaderReg

Data

HeaderStrobe

HeaderFIFO

DataByte 1

DataByte 2

DataByte n - 1

DataByte n

DataByte 0

DataByte 1

CSn:

Command strobe(s):

Read or write register(s):

Combinations:

CC115L

SWRS105B – MAY 2011 – REVISED JUNE 2014

www.ti.com

5.5.5

TX FIFO Access

The 64-byte TX FIFO is accessed through the 0x3F address. The TX FIFO is write-only and the R/W bit

should therefore be zero.

The burst bit is used to determine if the TX FIFO access is a single byte access or a burst access. The

single byte access method expects a header byte with the burst bit set to zero and one data byte. After

the data byte, a new header byte is expected; hence CSn can remain low. The burst access method

expects one header byte and then consecutive data bytes until terminating the access by setting CSn

high.

The following header bytes access the FIFO:

•

0x3F: Single byte access to TX FIFO

•

0x7F: Burst access to TX FIFO

When writing to the TX FIFO, the status byte (see Section 5.5.1) is output on SO for each new data byte

as shown in Figure 5-3. This status byte can be used to detect TX FIFO underflow while writing data to

the TX FIFO. Note that the status byte contains the number of bytes free before writing the byte in

progress to the TX FIFO. When the last byte that fits in the TX FIFO is transmitted on SI, the status byte

received concurrently on SO will indicate that one byte is free in the TX FIFO.

The TX FIFO may be flushed by issuing a SFTX command strobe. A SFTX command strobe can only be

issued in the IDLE, or TXFIFO_UNDERFLOW states. The TX FIFO is flushed when going to the SLEEP

state.

Figure 5-5 gives a brief overview of different register access types possible.

5.5.6

PATABLE Access

The 0x3E address is used to access the PATABLE, which is used for selecting PA power control settings.

The SPI expects one or two data bytes after receiving the address (the burst bit must be set if two bytes

are to be written). For OOK, two bytes should be written to PATABLE; the first byte after the address will

set the logic 0 power level and the second byte written will set the logic 1 power level. For all other

modulations formats, only one byte should be written to PATABLE. Use SmartRF Studio SWRC176 or

DN013 SWRA168 for recommended register values for a given output power.

The PATABLE can also be read by setting the R/W bit to 1. The read operation can be done as a single

byte or burst access, depending on how many bytes should be read (one or two). Note that pulling CSn

high will reset the index counter to zero, meaning that burst access needs to be used for reading/writing

the second PATABLE entry. For the same reason, if one byte is written to the PATABLE and this value is

to be read out, CSn must be set high before the read access in order to set the index counter back to

zero.

The content of the PATABLE is lost when entering the SLEEP state, except for the first byte, meaning that

if OOK is used, the PATABLE needs to be reprogrammed when waking up from SLEEP.

Figure 5-5. Register Access Types

Detailed Description

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