IS25LE512MG-RMLA2:PTY datasheet(126/194 Pages) ISSI

номер детали	IS25LE512MG-RMLA2:PTY

подробное описание детали	SERIAL FLASH MEMORY 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	194 Pages

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производитель	ISSI [Integrated Silicon Solution, Inc]

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126 / 194 page

IS25LE512MG

IS25WE512MG

Integrated Silicon Solution, Inc.- www.issi.com

126

Rev. A6

10/02/2025

8.43 FAST READ DTR MODE OPERATION (FRDTR, 0Dh or 4FRDTR, 0Eh)

The FRDTR/4FRDTR instruction is for doubling the data in and out. Signals are triggered on both rising and falling

edge of clock. The address is latched on both rising and falling edge of SCK, and data of each bit shifts out on both

rising and falling edge of SC. The 2-bit address can be latched-in at one clock, and 2-bit data can be read out at

one clock, which means one bit at the rising edge of clock, the other bit at the falling edge of clock.

The first address byte can be at any location. The address is automatically increased to the next higher address

after each byte of data is shifted out, so the whole memory can be read out in a single FRDTR/4FRDTR instruction.

The address counter rolls over to 0 when the highest address is reached.

• 0Dh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

• 0Dh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

• 0Eh is followed by a 4-byte address (A31-A0)

The sequence of issuing FRDTR/4FRDTR instruction is: CE# goes low → Sending FRDTR/4FRDTR instruction

code (1bit per clock) → 3-byte or 4-byte address on SI (2-bit per clock) as above → 8 dummy clocks (configurable,

default is 8 clocks) on SI → Data out on SO (2-bit per clock) → End FRDTR/4FRDTR operation via driving CE#

high at any time during data out.

While a Program/Erase/Write Status Register cycle is in progress, FRDTR/4FRDTR instruction will be rejected

without any effect on the current cycle.

IS25LE512MG-RMLA2:PTY датащи(PDF) 126 Page - Integrated Silicon Solution, Inc