IS25LE512MG-RMLA2:PTY datasheet(129/194 Pages) ISSI

129 / 194 page

IS25LE512MG

IS25WE512MG

Integrated Silicon Solution, Inc.- www.issi.com

129

Rev. A6

10/02/2025

FAST READ DTR OPERATION IN QPI MODE (FRDTR, 0Dh or 4FRDTR, 0Eh)

The FRDTR/4FRDTR instruction in QPI mode utilizes all four IO lines to input the instruction code so that only two

clocks are required, while the FRDTR/4FRDTR instruction in SPI mode requires that the byte-long instruction code

is shifted into the device only via IO0 (SI) line in eight clocks. In addition, subsequent address and data out are

shifted in/out via all four IO lines unlike the FRDTR/4FRDTR instruction. Eventually this operation is same as the

FRQDTR/4FRQDTR in QPI mode, but the only different thing is that AX mode is not available in the

FRDTR/4FRDTR operation in QPI mode.

• 0Dh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

• 0Dh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

• 0Eh is followed by a 4-byte address (A31-A0)

The sequence of issuing FRDTR/4FRDTR instruction in QPI mode is: CE# goes low → Sending FRDTR/4FRDTR

QPI instruction (4-bit per clock) → 24-bit or 32-bit address interleave on IO3, IO2, IO1 & IO0 (8-bit per clock) as

above → 6 dummy clocks (configurable, default is 6 clocks) → Data out interleave on IO3, IO2, IO1 & IO0 (8-bit

per clock) → End FRDTR/4FRDTR operation in QPI mode by driving CE# high at any time during data out.

If the FRDTR/4FRDTR instruction in QPI mode is issued while an Erase, Program or Write cycle is in process is in

progress (WIP=1), the instruction will be rejected without any effect on the current cycle.

Figure 8.85 FRDTR Sequence In QPI Mode (0Dh [EXTADD=0], 3-byte address)

Instruction

= 0Dh

CE #

SCK

3-byte Address

Mode 3

Mode 0

20 16 12

5 1

21 17 13

4 0

IO0

IO1

22 18 14

23 19 15

8 4 0

9 5 1

10 6 2

11 7 3

6 Dummy Cycles

IO2

IO3

6 2

7 3

5 1

4 0

6 2

7 3

Data

Out

Data

Out

...

Notes:

1. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.

2. Sufficient dummy cycles are required to avoid I/O contention.

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