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IS25LE512MG-RMLA2:PTY датащи(PDF) 123 Page - Integrated Silicon Solution, Inc

номер детали IS25LE512MG-RMLA2:PTY
подробное описание детали  SERIAL FLASH MEMORY 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
PDF  194 Pages
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производитель  ISSI [Integrated Silicon Solution, Inc]
домашняя страница  http://www.issi.com
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IS25LE512MG-RMLA2:PTY датащи(HTML) 123 Page - Integrated Silicon Solution, Inc

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IS25LE512MG
IS25WE512MG
Integrated Silicon Solution, Inc.- www.issi.com
123
Rev. A6
10/02/2025
8.40 INFORMATION ROW ERASE OPERATION (IRER, 64h)
Information Row Erase (IRER) instruction erases the data in the Information Row x (x: 0~3) array. Prior to the
operation, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is
automatically reset after the completion of the operation.
The sequence of IRER operation: Pull CE# low to select the device → Send IRER instruction code → Send three
address bytes → Pull CE# high. CE# should remain low during the entire instruction sequence. Once CE# is pulled
high, Erase operation will begin immediately. The internal control logic automatically handles the erase voltage and
timing.
Figure 8.80 IRER (Information Row Erase) Sequence
Instruction = 64h
23
CE #
SCK
SI
3
2
SO
1
0
3-byte Address
High Impedance
22
21
...
0
1
2
3
4
5
6
7
8
9
10
...
28
29
30
31
Mode 3
Mode 0



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