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TMP464

SBOS835C – MAY 2017 – REVISED OCTOBER 2019

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7.4 Device Functional Modes

7.4.1 Shutdown Mode (SD)

The TMP464 shutdown mode enables the user to save maximum power by shutting down all device circuitry

other than the serial interface, and reducing current consumption to typically less than 0.3 μA; see Figure 11.

Shutdown mode is enabled when the shutdown bit (SD, bit 5) of the Configuration Register is HIGH; the device

shuts down immediately. When the SD bit is LOW, the device maintains a continuous-conversion state.

7.5 Programming

7.5.1 Serial Interface

The TMP464 device operates only as a slave device on the two-wire bus (I2C or SMBus). Connections to either

bus are made using the open-drain I/O lines, SDA, and SCL. The SDA and SCL pins feature integrated spike

suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP464

device supports the transmission protocol for fast (1 kHz to 400 kHz) and high-speed (1 kHz to 2.56 MHz)

modes. All data bytes are transmitted MSB first.

While the TMP464 device is unpowered bus traffic on SDA and SCL may continue without any adverse effects to

the communication or to the TMP464 device itself. As the TMP464 device is powering up, the device does not

load the bus, and as a result the bus traffic may continue undisturbed.

7.5.1.1 Bus Overview

The TMP464 device is compatible with the I2C or SMBus interface. In I2C or SMBus protocol, the device that

initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be

controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the

start and stop conditions.

To address a specific device, a start condition is initiated. A start condition is indicated by pulling the data line

(SDA) from a high-to-low logic level when SCL is high. All slaves on the bus shift in the slave address byte, with

the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the addressed

slave responds to the master by generating an acknowledge (ACK) bit and pulling SDA low.

Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit (ACK). During

data transfer, SDA must remain stable when SCL is high. A change in SDA when SCL is high is interpreted as a

control signal. The TMP464 device has a word register structure (16-bit wide), with data writes always requiring

two bytes. Data transfer occurs during the ACK at the end of the second byte.

After all data are transferred, the master generates a stop condition. A stop condition is indicated by pulling SDA

from low to high when SCL is high.