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TDP2004 датащи(PDF) 9 Page - Texas Instruments |
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TDP2004 датащи(HTML) 9 Page - Texas Instruments |
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9 / 34 page ![]() 5.6 High Speed Electrical Characteristics (continued) over operating free-air temperature and voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT XT Channel to channel xtalk (between adjacent active channels, FEXT Minimum over 50.0MHz to 10.0Ghz range, normalized to EQ gain of 0dB –38 dB LINEARITY- DC Output DC linearity 1650 mVpp LINEARITY- AC Output AC linearity at GAIN = L4 8Gbps 1250 mVpp LINEARITY- AC Output AC linearity at GAIN = L4 16Gbps 1200 mVpp LINEARITY- AC Output AC linearity at GAIN = L4 20Gbps 1100 mVpp 5.7 SMBUS/I2C Timing Charateristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Target Mode tSP Pulse width of spikes which must be suppressed by the input filter 50 ns tHD-STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs THIGH HIGH period of the SCL clock 0.6 µs tSU-STA Setup time for a repeated START condition 0.6 µs tHD-DAT Data hold time 0 µs TSU-DAT Data setup time 0.1 µs tr Rise time of both SDA and SCL signals Pullup resistor = 4.7kΩ, Cb = 10pF 120 ns tf Fall time of both SDA and SCL signals Pullup resistor = 4.7kΩ, Cb = 10pF 2 ns tSU-STO Setup time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tVD-DAT Data valid time 0.9 µs tVD-ACK Data valid acknowledge time 0.9 µs Cb Capacitive load for each bus line 400 pF Controller Mode fSCL-M SCL clock frequency 303 kHz tLOW-M SCL low period 1.90 µs THIGH-M SCL high period 1.40 µs tSU-STA-M Setup time for a repeated START condition 2 µs tHD-STA-M Hold time (repeated) START condition. After this period, the first clock pulse is generated 1.5 µs TSU-DAT-M Data setup time 1.4 µs tHD-DAT-M Data hold time 0.5 µs tR-M Rise time of both SDA and SCL signals Pullup resistor = 4.7kΩ, Cb = 10pF 120 ns www.ti.com TDP2004-Q1 SNLS787 – SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TDP2004-Q1 |
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