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TDP2004 датащи(PDF) 3 Page - Texas Instruments

номер детали TDP2004
подробное описание детали  TDP2004-Q1 Automotive Four-Channel 20Gbps DisplayPort 2.1 Linear Redriver
PDF  34 Pages
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производитель  TI2 [Texas Instruments]
домашняя страница  https://www.ti.com
Logo TI2 - Texas Instruments

TDP2004 датащи(HTML) 3 Page - Texas Instruments

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4 Pin Configuration and Functions
Thermal
pad
33
GND
34
SEL
35
NC
36
NC
37
NC
38
PD
39
DONEn
40
GND
13
GND
14
READ_ENn
15
EQ0/ADDR0
16
EQ1/ADDR1
17
MODE
18
TEST/SCL
19
GAIN/SDA
20
GND
Not to scale
Figure 4-1. RGF Package, 40-Pin VQFN (Top View)
Table 4-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
DONEn
39
O, 3.3V open
drain
In SMBus/I2C Controller mode:
Indicates the completion of a valid EEPROM register load operation. External pullup
resistor such as 4.7kΩ required for operation.
High: External EEPROM load failed or incomplete
Low: External EEPROM load successful and complete
In SMBus/I2C Target/Pin mode:
This output is High-Z. The pin can be left floating.
MODE
17
I, 5-level
Sets device control configuration modes. 5-level IO pin as provided in Table 6-3. The
pin can be exercised at device power up or in normal operation mode.
L0: Pin mode – device control configuration is done solely by strap pins.
L1: SMBus/I2C Controller mode – device control configuration is read from external
EEPROM. When the TDP2004-Q1 finishes reading from the EEPROM successfully,
Don En pin is pulled LOW. SMBus/I2C Target operation is available in this mode
before, during or after EEPROM reading. Note: during EEPROM reading if the external
SMBus/I2C Controller wants to access TDP2004-Q1 registers, the external controller
must support arbitration.
L2: SMBus/I2C Target mode – device control configuration is done by an external
controller with SMBus/I2C Controller.
L3 and L4 (Float): RESERVED – TI internal test modes.
EQ0 / ADDR0
15
I, 5-level
In Pin mode:
Sets receiver linear equalization (CTLE) boost for channels 0-3 as provided in Table
6-1. These pins are sampled at device power up only.
In SMBus/I2C mode:
Sets SMBus / I2C Target address as provided in Table 6-4. These pins are sampled at
device power up only.
EQ1 / ADDR1
16
I, 5-level
GAIN / SDA
19
I, 5-level / I/O,
3.3V
LVCMOS,
open drain
In Pin mode:
Flat gain (DC and AC) from the input to the output of the device for channels 0-3. The
pin is sampled at device power up only.
In SMBus/I2C mode:
3.3V SMBus/I2C data. External 1kΩ to 5kΩ pullup resistor is required as per SMBus /
I2C interface standard.
www.ti.com
TDP2004-Q1
SNLS787 – SEPTEMBER 2025
Copyright © 2025 Texas Instruments Incorporated
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Product Folder Links: TDP2004-Q1



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