UCC28056ADBVT datasheet(39/55 Pages) TI2

39 / 55 page

OS11

OS12

BLK

27.95 k

OS11

3.24 M

9.72 M

OS11

OS12

OS2

BLK

OS12

OS2

108

Out Re g

OS11

OS12

OS2

OSRe g

OS2

156

OSRe g

Out Re g

OS1

OSRe g

OSBias

390 V

39 M

100 nA

OSRe g

OSBias

OS1

OSRe g

Out Re g

OSDiv

OS1

OS2

u ¨

OS1

Out Re g

OSRe g

OS2

ZC3

10pF

ZC3

3 k

UCC28056

www.ti.com

SLUSD37E – OCTOBER 2017 – REVISED NOVEMBER 2019

Product Folder Links: UCC28056

Submit Documentation Feedback

For this example design, the following values were selected for the RC filter to attenuate switching edge spikes.

(68)

(69)

9.2.2.4 VOSNS Pin

The VOSNS pin voltage is applied to the inverting input of an internal trasnconductance error amplifier. A fixed

reference voltage (VOSReg) being applied to the non-inverting input. The error amplifier has high gain hence in

steady-state, assuming VCOMP < 5-V, average voltage on the VOSNS pin must be approximately equal to the

reference voltage (VOSReg). Output voltage regulation set point (VOutReg) is therefore determined by the external

resistor divider network connecting the output voltage to the VOSNS pin according to the following expression.

(70)

The resistive divider that feeds the VOSNS pin makes a significant contribution to the unloaded input power.

Higher resistor values reduce power consumption of the divider.

(71)

Regulation accuracy degrades with increased resistor values due to the effect of VOSNS pin bias current

(IOSBias).

(72)

To ensure that VOSNS pin bias current degrades output voltage regulation by less than 1%, the upper voltage

divider resistor value must be constrained as show in Equation 73.

(73)

Equation 73 confirms that reduction of the VOSNS divider dissipation to below 4 mW does not negatively

affecting the regulation accuracy.

The PFC stage, of this design example, is to be followed by an LLC stage, that is controlled by UCC256301

device. The UCC28056 controller and the UCC256301 device operate together to form a complete off-Line

power supply system with excellent light-load efficiency and standby power. To limit no-load input power a single

resistor divider feeds both the VOSNS pin (UCC28056) and the BLK pin (UCC256301). A resistor divider with

two taps is required because the UCC28056 requires a different divide ratio (KOS) to that required for the

UCC256301 device (KBLK). The upper divider resistor (ROS1) is divided into two parts (ROS11, ROS12) to achieve

the additional tap.

(74)

(75)

For this design example select an upper divider resistor made up of three series-connected, 3.24-M

Ω, 1206 SMT

resistors. This compact and cost-effective design produces a suitable high-voltage resistor. If a single resistor is

preferred, use a high voltage type, rated for the maximum voltage that can appear across the output capacitor

during a Line surge test.

(76)

Solving Equation 74 and Equation 75 simultaneously results in:

(77)

UCC28056ADBVT датащи(PDF) 39 Page - Texas Instruments

UCC28056ADBVT датащи(HTML) 39 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

датащи скачать

ссылки URL