UCC28056ADBVT datasheet(21/55 Pages) TI2

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RZC1

RZC2

IL(t)

RDSON x IL(t)

RCS x IL(t)

VZC(t)

GND

ZCD/CS

ZC2

DSON

ZC1

ZC2

UCC28056

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SLUSD37E – OCTOBER 2017 – REVISED NOVEMBER 2019

Product Folder Links: UCC28056

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Feature Description (continued)

8.3.5.1 Supply Undervoltage Lockout

Supply undervoltage lockout (UVLO) protection ensures that the controller operates only while the supply voltage

is in a range that ensures correct operation and adequate Gate drive amplitude for the power switch.

The controller remains in a dormant state, consuming little ICC current (ICC_Startup), until the VCC pin voltage

exceeds VCCStart. Once VCCStart is exceeded, the controller wakes into its Stopb state. After waking, the controller

proceeds with its normal start-up process.

The controller stops switching if the VCC pin voltage falls below VCCStop for a longer period than TUVLOBlk. The

controller then returns to a dormant condition. During this dormant period, the controller consumes a relatively

small amount of supply current (ICC) until it exceeds the VCCStart threshold again.

8.3.5.2 Two Level Over-Current Protection

The UCC28056 controller includes two overcurrent protection mechanisms to deliver safe robust protection

without danger of false tripping during operating transients. During the ON period of the switch, a current sense

resistor (RCS) connected in the source lead of the power switch senses the inductor current. The ZCD/CS pin

detects the voltage across the current sense resistor. Equation 12 dscribes the current sense voltage signal

applied to the ZCD/CS pin. Typically the second term in the bracket is much smaller than current sense resitance

value (RCS ) and can be neglected.

(12)

Figure 23. Equivalent Circuit of External Current Sense Network

8.3.5.2.1

Cycle-by-Cycle Current Limit Ocp1

Cycle-by-cycle peak current protection (Ocp1) terminates the on-time (TON) duration early if the current sense

voltage rises above 0.5 V. This current protection method limits the peak inductor current, thus avoiding inductor

saturation or damage to the power stage. When cycle-by-cycle current limit is active, it impacts Line current

distortion, but in all other respects normal switching operation continues and the controller maintains output

regulation.

The controller applies leading edge blanking to the current sense voltage signal. This application ensures that the

leading edge current spike caused by discharging CDE does not cause the Ocp1 comparator to terminate the

DRV pulse too early.

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