ICS853014

LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

10

ICS853014BG REV. DNOVEMBER 12, 2007

LVPECL Clock Input Interface

The PCLK/PCLK accepts LVPECL, LVDS, CML, SSTL and other

examples for the HiPerClockS PCLK/PCLK input driven by the

most common driver types. The input interfaces suggested here

are examples only. If the driver is from another vendor, use their

termination recommendation. Please consult with the vendor of the

driver component to confirm the driver termination requirements.

Figure 3A. HiPerClockS PCLK/PCLK Input

Driven by an Open Collector CML Driver

Figure 3C. HiPerClockS PCLK/PCLK Input

Driven by a 3.3V LVPECL Driver

Figure 3E. HiPerClockS PCLK/PCLK Input

Driven by an SSTL Driver

Figure 3B. HiPerClockS PCLK/PCLK Input

Driven by a Built-In Pullup CML Driver

Figure 3D. HiPerClockS PCLK/PCLK Input Driven by

a 3.3V LVPECL Driver with AC Couple

Figure 3F. HiPerClockS PCLK/PCLK Input

Driven by a 3.3V LVDS Driver

PCLK

nPCLK

HiPerClockS

PCLK/nPCLK

CML

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

3.3V

R1

50

R2

50

R3

125

R4

125

R1

84

R2

84

3.3V

Zo = 50

Ω

Zo = 50

Ω

PCLK

nPCLK

3.3V

3.3V

LVPECL

HiPerClockS

Input

PCLK

nPCLK

HiPerClockS

PCLK/nPCLK

SSTL

2.5V

Zo = 60

Ω

Zo = 60

Ω

2.5V

3.3V

R1

120

R2

120

R3

120

R4

120

3.3V

R1

100

CML Built-In Pullup

PCLK

nPCLK

3.3V

HiPerClockS

PCLK/nPCLK

Zo = 50

Ω

Zo = 50

Ω

R3

84

R4

84

R1

125

R2

125

R5

100 - 200

R6

100 - 200

PCLK

nPCLK

3.3V LVPECL

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

3.3V

HiPerClockS

PCLK/nPCLK

C1

C2

PCLK

nPCLK

3.3V

HiPerClockS

PCLK/nPCLK

R3

1k

R4

1k

R1

1k

R2

1k

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

C1

C2

R5

100

LVDS