ICS853014

LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

3

ICS853014BG REV. DNOVEMBER 12, 2007

Function Tables

Table 3A. Control Input Function Table

After EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1.

In the active mode, the state of the outputs are a function of the PCLK0/PCLK0 and PCLK1/PCLK1 inputs as described in Table 3B.

Figure 1. EN Timing Diagram

Table 3B. Clock Input Function Table

Inputs

Outputs

EN

CLK_SEL

Selected Source

Q0:Q4

Q0:Q4

1

0

PCLK0, PCLK0

Disabled; Low

Disabled; High

1

1

PCLK1, PCLK1

Disabled; Low

Disabled; High

0

0

PCLK2, PCLK2

Enabled

Enabled

0

1

PCLK3, PCLK3

Enabled

Enabled

Inputs

Outputs

Input to Output Mode

Polarity

PCLK0 or PCLK1

PCLK0 or PCLK1

Q0:Q4

Q0:Q4

0

1

LOW

HIGH

Differential to Differential

Non-Inverting

1

0

HIGH

LOW

Differential to Differential

Non-Inverting

0

Biased; NOTE 1

LOW

HIGH

Single-Ended to Differential

Non-Inverting

1

Biased; NOTE 1

HIGH

LOW

Single-Ended to Differential

Non-Inverting

Biased; NOTE 1

0

HIGH

LOW

Single-Ended to Differential

Inverting

Biased; NOTE 1

1

LOW

HIGH

Single-Ended to Differential

Inverting

Enabled

Disabled

PCLK0, PCLK1

EN

Q0:Q4

Q0:Q4

PCLK0, PCLK1