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REF3312, REF3318, REF3320, REF3325, REF3330, REF3333

SBOS392H – AUGUST 2007 – REVISED AUGUST 2019

www.ti.com

Product Folder Links: REF3312 REF3318 REF3320 REF3325 REF3330 REF3333

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Copyright © 2007–2019, Texas Instruments Incorporated

Typical Applications (continued)

10.2.1.1 Design Requirements

The design requirements are as follows:

•

Supply voltage: 3.3 V

•

Maximum input voltage: ±6 V

•

Specified input voltage: ±5 V

•

ADC reference voltage: 1.25 V

10.2.1.2 Detailed Design Procedure

Figure 19 depicts a simplified schematic for this design showing the MSP430 ADC inputs and full input

conditioning circuitry. The ADC is configured for a bipolar measurement where final conversion result is the

differential voltage, VDIFF, between the positive and negative ADC inputs, A1+ and A1–. The bipolar, ground-

referenced input signal must be level-shifted and attenuated by the op amp so that the output is biased to VREF /

2 and has a differential voltage that is within the ±VREF / 2 input range of the ADC. The transfer function for the

op-amp circuit simplifies to Equation 4.

where

•

R1 = R4

•

R5 = R2 || R3

(4)

The voltage applied to the negative ADC input, A1–, is based on the resistor divider formed by R6 and R7 and is

set to VREF / 2 by setting R6 equal to R7, as shown in Equation 5.

(5)

10.2.1.2.1

Op Amp Level-Shift Design

The ratio of R2, R3, and the VREF voltage determines the voltage on the output of the op amp when the

differential input is 0 V. Select the components so that VOUT is equal to the VREF / 2 voltage when VIN is equal to

0 V, as shown in Equation 6.

where

•

VIN = 0 V

•

R2 = R3

(6)

Solve for the value of R5 by setting R3 equal to R2 in Equation 4, as shown in Equation 7:

(7)

10.2.1.2.2

Differential Input Attenuator Design

VDIFF is the difference between the two inputs, as shown in Equation 8:

(8)