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16

REF3312, REF3318, REF3320, REF3325, REF3330, REF3333

SBOS392H – AUGUST 2007 – REVISED AUGUST 2019

www.ti.com

Product Folder Links: REF3312 REF3318 REF3320 REF3325 REF3330 REF3333

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Copyright © 2007–2019, Texas Instruments Incorporated

The 3.3-V system supply voltage that powers the MSP430 can also supply other devices, and therefore may

have regulation and noise issues. The REF3330 creates an accurate and stable 3.0 V output used by the op

amp, REF3312, and other low-power analog circuitry. The REF33xx series has a drop-output voltage of VOUT +

200 mV; therefore, as long as the input supply remains above 3.2 V, the REF3330 produces a regulated 3.0 V

output. The output current for the REF33xx series is specified at ±5 mA, as shown in Figure 9, and is sufficient

for the REF3312 and a low-power op amp.

10.2.1.2.4.2

Op Amp

The OPA317 op amp is used because of low offset voltage, low offset voltage drift, CMRR, and low power

consumption. The dc specifications for the OPA317 can be seen in the OPA317 data sheet, SBOS682, available

for download from www.ti.com. The maximum offset of 100 µV accounts for only 0.001% of the full-scale signal,

and the low-drift reduces temperature drift effects. Therefore, as previously mentioned, most of the error in this

design is from the reference accuracy and passive component tolerances.

10.2.1.2.5

Input Attenuation and Level Shifting

For this design, the bipolar ±5-V input must be attenuated and level shifted so the differential voltage is within the

input range of ±VREF / 2, or ±0.625 V. The accuracy of the op amp output and ADC input may degrade near the

supply rails and VREF voltage, so the output is designed to produce a 0.125 V to 1.125 V output, or ±0.5 V for a

±5 V input. Scaling the output this way also increases the allowable input range to ±6 V, and allows for some

underscale and overscale voltage measurement and protection.

Use Equation 12 to scale the ±5-V input to a ±0.5-V differential voltage, as shown in Equation 15.

where

•

R1 = R4 = 100 kΩ

(15)

R1 and R4 dominate the input impedance for this design and are therefore selected to be 100 kΩ. Higher values

can be selected to increase the input impedance at the expense of input noise.

With the value for R2 and R3 selected as 20 kΩ, the value for R5 is calculated, as shown in Equation 16:

where

•

R2 = R3 = 20 kΩ

(16)

In order for A1– to equal to VREF / 2, R6 must equal R7. Two 47-kΩ resistors are used in order to conserve power

without creating an impedance too weak to drive the ADC input.

10.2.1.2.6

Input Filtering

The MSP430 ADC is configured to run from the 1.1-MHz SMCLK with an oversampling rate (OSR) of 256,

yielding a sample rate of roughly 4.3 kHz. The input filter cutoff frequency is set to 1 kHz in order to limit the input

signal bandwidth, as shown in Equation 17. R8 is 1 kΩ in order to provide isolation from the capacitive load of the

low-pass filter, thereby reducing stability concerns.

where

•

(17)

Reduce C1 to 150 nF so that it is a standard value.

The A1– input of the delta-sigma (ΔΣ) converter is not buffered, and therefore requires a large capacitor to

supply the charge for the internal sampling capacitor. A 47-μF capacitor is selected, resulting in the cutoff

frequency illustrated in Equation 18.