PCM2704CDB.B datasheet(29/53 Pages) TI2

29 / 53 page

PCM2704C, PCM2705C, PCM2706C, PCM2707C

www.ti.com

SBFS036B – MAY 2015 – REVISED AUGUST 2015

9.6 Register Maps

9.6.1 SPI Register (PCM2705C/7C)

NOTE

Contents of the power attribute and max power must be consistent with the actual

application circuit configuration (the PSEL setting and the actual power usage from VBUS

of the USB connector); otherwise, it may cause improper or unexpected PCM2705C/7C

operation.

Figure 34. SPI Register Description

ADDR

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. SPI Register Field Descriptions(1)

Bit

Field

Type

Reset

Description

Determines the function of the lower 8-bit data. Table 9 summarizes the

functionality of ST and ADDR bit combinations.

0: HID status write

1: Descriptor ROM data write

Starts write operation for internal descriptor reprogramming (active high)

This bit resets the descriptor ROM address counter and indicates that subsequent

words should be ROM data (described in External ROM Example). 456 bits of ROM

ADDR

data must be continuously followed after this bit has been asserted. The data bits

must be sent from LSB (D0) to MSB (D7).

To set ADDR high, ST must be set low. Note that the lower 8 bits are still active as an

HID status write when ST is set low.

ST = 0 (HID status write); Reports extended command status to the host (active high)

ST = 1 (ROM data write); Internal descriptor ROM data, D0:LSB

ST = 0 (HID status write); Reports play/pause HID status to the host (active high)