PCM1795DBRG4 datasheet(30/68 Pages) TI2

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PCM1795

SLES248A – MAY 2009 – REVISED MARCH 2015

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When R/W = 1, a read operation is performed.

Default value: 0

7.6.1.3.4

ATLD: Attenuation Load Control

This bit is available for read and write.

Default value: 0

Table 12. ATLD

ATLD

ATTENUATION CONTROL SETTING

ATLD = 0

Attenuation control disabled (default)

ATLD = 1

Attenuation control enabled

The ATLD bit is used to enable loading of the attenuation data contained in registers 16 and 17. When ATLD =

0, the attenuation settings remain at the previously programmed levels, ignoring new data loaded from registers

16 and 17. When ATLD = 1, attenuation data written to registers 16 and 17 is loaded normally.

7.6.1.3.5

FMT[2:0]: Audio Interface Data Format

These bits are available for read and write.

Default value: 101

Table 13. FMT[2:0]

FMT[2:0]

AUDIO DATA FORMAT SELECTION

000

16-bit standard format, right-justified data, BCK

≥ x32 fS

001

32-bit standard format, right-justified data, BCK

≥ x64 fS

010

24-bit standard format, right-justified data, BCK

≥ x48 fS

011

24-bit MSB-first, left-justified format data, BCK

≥ x48 fS

100

32-bit I2S format data, BCK

≥ x64 fS

101

24-bit I2S format data (default), BCK

≥ x48 fS

110

Reserved

111

Reserved

The FMT[2:0] bits are used to select the data format for the serial audio interface.

For the external digital filter interface mode (DFTH mode), this register is operated as shown in Application for

External Digital Filter Interface.

7.6.1.3.6

DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function

These bits are available for read and write.

Default value: 00

Table 14. DMF[1:0]

DMF[1:0]

DE-EMPHASIS SAMPLING FREQUENCY SELECTION

Disabled (default)

48 kHz

44.1 kHz

32 kHz

The DMF[1:0] bits are used to select the sampling frequency used by the digital de-emphasis function when it is

enabled by setting the DME bit. The de-emphasis curves are shown in Typical Characteristics.

For the DSD mode, analog FIR filter performance can be selected using this register. A register map and filter

response plots are shown in Application For DSD Format (DSD Mode) Interface.

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