ONET1130EC datasheet(4/64 Pages) TI2

4 / 64 page

ONET1130EC

SLLSEJ3A – JUNE 2015 – REVISED JULY 2015

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Pin Functions (continued)

NUMBER

NAME

Type

DESCRIPTION

2-wire interface serial data input. Requires an external 4.7-k

Ω to10-kΩ pull-up resistor

SDA

Digital-in/out

to VCC. This pin is 3.3-V tolerant.

2-wire interface serial clock input. Requires an external 4.7-k

Ω to10-kΩ pull-up

SCK

Digital-in

resistor to VCC. This pin is 3.3-V tolerant.

Disables both bias and modulation currents when set to high state. Includes a 250-k

pull-up resistor to VCC. Requires an external 4.7 k

Ω to 10 kΩ pull-up resistor to VCC

TX_DIS

Digital-in

for proper operation Toggle to reset a fault condition. This is an ORed function with

the TXBIASEN bit (bit 2 in register 1). This pin is 3.3-V tolerant.

Non-inverted transmitter data input. On-chip differentially 100

Ω terminated to TXIN–.

TXIN+

Analog-in

Must be AC coupled.

Inverted transmitter data input. On-chip differentially 100

Ω terminated to TXIN+. Must

TXIN–

Analog-in

be AC coupled.

TX_LF

Analog-in

Transmitter loop filter capacitor.

Transmitter fault detection flag. High level indicates that a fault has occurred. Open

TX_FLT

Digital-out

drain output. Requires an external 4.7 k

Ω to 10 kΩ pull-up resistor to VCC for proper

operation. This pin is 3.3-V tolerant.

Inverted transmitter data output. Internally terminated in single-ended operation

TXOUT–

CML-out

mode.

TXOUT+

CML-out

Non-Inverted transmitter data output.

VCC_RX

27, 30

Supply

2.5 V ± 5% supply for the receiver.

VCC_TX

11, 14

Supply

2.5 V ± 5% supply for the transmitter.

VDD

Supply

2.5 V ± 5% supply for the digital circuitry.

Exposed Pad

Exposed die pad. Solder to the PCB.

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