LP5569 datasheet(25/93 Pages) TI2

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ack from slave

start

MSB Chip Addr LSB

SCL

ack from slave

MSB Register Addr LSB

MSB

Data

LSB

stop

ack from slave

nack from master

repeated start

data from slave

SDA

start

id =32h

w ack

address = 3Fh

ack

r ack

address 3Fh data

nack

stop

MSB Chip Address LSB

id = 32h

LP5569

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SNVSAP8A – JULY 2017 – REVISED SEPTEMBER 2017

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6. The master device generates a repeated-start condition.

7. The master device sends the slave address (7 bits) and the data direction bit (R/W = 1).

8. The slave device sends an acknowledge signal if the slave address is correct.

9. The slave device sends the data byte from the addressed register.

10. If the master device sends an acknowledge signal, the control register address is incremented by 1. The

slave device sends the data byte from the addressed register.

11. The read cycle ends when the master device does not generate an acknowledge signal after a data byte

and generates a stop condition.

ID = chip address = 32h for the LP5569 device

Figure 24. Read Cycle (R = Read; SDA = 1)

8.5.1.7 Auto-Increment Feature

The auto-increment feature allows writing several consecutive registers within one transmission. Every time an

‑bit word is sent to the LP5569 device, the internal address index counter is incremented by 1, and the next

EN_AUTO_INCR bit = 0 in the MISC register (address 2Fh).

8.5.2 Execution Engine Programming

The LP5569 device provides flexibility and programmability for dimming and sequencing control. Each LED can

be controlled directly and independently through the serial bus, or LED drivers can be grouped together for pre-

programmed flashing patterns.

The LP5569 device has three independent program execution engines, so it is possible to form three

independently programmable LED banks. LED drivers can be grouped based on their function so that, for

example, the first bank of drivers can be assigned to the keypad illumination, the second bank to the funlights,

and the third group to the indicator LED(s). Each bank can contain 1 to 9 LED driver outputs. Instructions for

program execution engines are stored in the program memory. The total amount of the program memory is 255

instructions, and the user can allocate the instructions as required by the engines; however, a single engine can

only allocate up to ½ the memory (128 instructions).

8.5.2.1 SRAM Memory

The LP5569 device has internal SRAM for the three LED engines. SRAM can contain up to 255 16-bit

instructions (addresses 0 through 254) with a maximum size of 128 16-bit instructions for a single engine. SRAM

memory address 255 is reserved and must not be allocated to any LED engine. Memory allocation among the

three LED engines is done dynamically, so that each LED engine has a separate start address and program

counter (PC) that are set in the ENGINEx_PROG_START registers (addresses 4Bh, 4Ch, 4Dh) and

ENGINEx_PC registers (addresses 30h, 31h, 32h). This allows flexible memory allocation among the LED

engines, and multiple engines can recall the same memory address. The program counter uses relative memory

addressing; when the PC is zero the engine is executing an instruction at its start address.

The SRAM is loaded via the I2C interface in 33-byte-length pages. The first byte contains the program-memory-

page-select (address 4Fh) followed by up to 32 bytes containing compiled program execution engine instructions

(address 50h thru 6Fh). Engines must be set to load the program mode (register 01h) before writing the SRAM.

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