STM32L443CC datasheet(55/215 Pages) STMICROELECTRONICS

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DS11421 Rev 4

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STM32L443CC STM32L443RC STM32L443VC

Functional overview

automatic trimming mode. The synchronization for this oscillator can be taken from the USB

data stream itself (SOF signalization) which allows crystal less operation.

3.35

Clock recovery system (CRS)

The STM32L443xx devices embed a special block which allows automatic trimming of the

internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device

operational range. This automatic trimming is based on the external synchronization signal,

which could be either derived from USB SOF signalization, from LSE oscillator, from an

external signal on CRS_SYNC pin or generated by user software. For faster lock-in during

startup it is also possible to combine automatic trimming with manual trimming action.

3.36

Quad SPI memory interface (QUADSPI)

The Quad SPI is a specialized communication interface targeting single, dual or quad SPI

flash memories. It can operate in any of the three following modes:

•

Indirect mode: all the operations are performed using the QUADSPI registers

•

Status polling mode: the external flash status register is periodically read and an

interrupt can be generated in case of flag setting

•

Memory-mapped mode: the external Flash is memory mapped and is seen by the

system as if it were an internal memory

Both throughput and capacity can be increased two-fold using dual-flash mode, where two

Quad SPI flash memories are accessed simultaneously.

The Quad SPI interface supports:

•

Three functional modes: indirect, status-polling, and memory-mapped

•

Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two

flash memories in parallel.

•

SDR and DDR support

•

Fully programmable opcode for both indirect and memory mapped mode

•

Fully programmable frame format for both indirect and memory mapped mode

•

Each of the 5 following phases can be configured independently (enable, length,

single/dual/quad communication)

–

Instruction phase

–

Address phase

–

Alternate bytes phase

–

Dummy cycles phase

–

Data phase

•

Integrated FIFO for reception and transmission

•

8, 16, and 32-bit data accesses are allowed

•

DMA channel for indirect mode operations

•

Programmable masking for external flash flag management

•

Timeout management

•

Interrupt generation on FIFO threshold, timeout, status match, operation complete, and

access error

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