LM5175PWPR datasheet(4/43 Pages) TI2

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LM5175

SNVSA37A – OCTOBER 2015 – REVISED MAY 2016

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Pin Functions

DESCRIPTION

NAME

HTSSOP

QFN

EN/UVLO

Enable pin. For EN/UVLO < 0.4 V, the LM5175 is in a low current shutdown mode. For 0.7 V <

EN/UVLO < 1.23 V, the controller operates in standby mode in which the VCC regulator is enabled but

the PWM controller is not switching. For EN/UVLO > 1.23 V, the PWM function is enabled, provided

VCC exceeds the VCC UV threshold.

VIN

The input supply pin to the IC. Connect VIN to a supply voltage between 3.5 V and 42 V.

VISNS

VIN sense input. Connect to the input capacitor.

MODE

Mode = GND, DCM, Hiccup Disabled

(Set RMODE resistor to GND = 0 Ω)

Mode = 1.00 V, DCM, Hiccup Enabled

(Set RMODE resistor to GND = 49.9 kΩ)

Mode = 1.85 V, CCM, Hiccup Enabled

(Set RMODE resistor to GND = 93.1 kΩ)

Mode = VCC, CCM, Hiccup Disabled

(Set RMODE resistor to VCC = 0 Ω)

DITH

A capacitor connected between the DITH pin and AGND is charged and discharged with a 10 uA

current source. As the voltage on the DITH pin ramps up and down the oscillator frequency is

modulated between –5% and +5% of the nominal frequency set by the RT resistor. Grounding the

DITH pin will disable the dithering feature. In the external Sync mode, the DITH pin voltage is ignored.

RT/SYNC

Switching frequency programming pin. An external resistor is connected to the RT/SYNC pin and

AGND to set the switching frequency. This pin can also be used to synchronize the PWM controller to

an external clock.

SLOPE

A capacitor connected between the SLOPE pin and AGND provides the slope compensation ramp for

stable current mode operation in both buck and boost mode.

Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start time.

COMP

Output of the error amplifier. An external RC network connected between COMP and AGND

compensates the regulator feedback loop.

AGND

Analog ground of the IC.

Feedback pin for output voltage regulation. Connect a resistor divider network from the output of the

converter to the FB pin.

VOSNS

VOUT sense input. Connect to the output capacitor.

ISNS(–)

ISNS(+)

Input or Output Current Sense Amplifier inputs. An optional current sense resistor connected between

ISNS(+) and ISNS(–) can be located either on the input side or on the output side of the converter. If

the sensed voltage across the ISNS(+) and ISNS(-) pins reaches 50 mV, a slow Constant Current (CC)

control loop becomes active and starts discharging the soft-start capacitor to regulated the drop across

ISNS(+) and ISNS(-) to 50 mV. Short ISNS(+) and ISNS(-) together to disable this feature.

CSG

The negative or ground input to the PWM current sense amplifier. Connect directly to the low-side

(ground) of the current sense resistor.

The positive input to the PWM current sense amplifier.

PGOOD

Power Good open drain output. PGOOD is pulled low when FB is outside a 0.8 V ±10% regulation

window.

SW2

SW1

The boost and the buck side switching nodes respectively.

HDRV2

HDRV1

Output of the high-side gate drivers. Connect directly to the gates of the high-side MOSFETs.

BOOT2

BOOT1

An external capacitor is required between the BOOT1, BOOT2 pins and the SW1, SW2 pins

respectively to provide bias to the high-side MOSFET gate drivers.

LDRV2

LDRV1

Output of the low-side gate drivers. Connect directly to the gates of the low-side MOSFETs.

PGND

Power ground of the IC. The high current ground connection to the low-side gate drivers.

VCC

Output of the VCC bias regulator. Connect capacitor to ground.

BIAS

Optional input to the VCC bias regulator. Powering VCC from an external supply instead of VIN can

reduce power loss at high VIN. For VBIAS > 8 V, the VCC regulator draws power from the BIAS pin. The

BIAS pin voltage must not exceed 40 V.

PowerPAD

™

The PowerPAD should be soldered to the analog ground. If possible, use thermal vias to connect to a

PCB ground plane for improved power dissipation.

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