DITH

MOD

10 A

C

F

0.24 V

P

u

SS

ss

0.8 V C

t

5 A

u

P

UV2

UV1

IN

UV2

UV

R

1.23 V

R

59.5 k

V

1.5 A R

1.23 V

u

:

P u

SLOPE

SLOPE

SENSE

CS

L1

4.7 H

C

gm

2 S

235 pF

R

A

8 m

5

P

u

P u

u

: u

2

IN(MIN)

RSENSE(MAX)

SENSE

SENSE

OUT

V

170mV

P

R

1

1.8 W

R

V

§

·

§

·

˜

˜ ¨

¸

¨

¸

¨

¸

©

¹

©

¹

24

LM5175

SNVSA37A – OCTOBER 2015 – REVISED MAY 2016

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Product Folder Links: LM5175

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Copyright © 2015–2016, Texas Instruments Incorporated

The maximum power dissipation in RSENSE happens at VIN(MIN):

(24)

Based on this, select the current sense resistor with power rating of 2 W or higher.

For some application circuits, it may be required to add a filter network to attenuate noise in the CS and CSG

sense lines. Please see Figure 24 for typical values. The filter resistance should not exceed 100 Ω.

9.2.2.8 Slope Compensation

For stable current loop operation and to avoid sub-harmonic oscillations, the slope capacitor should be selected

based on Equation 25:

(25)

This slope compensation results in “dead-beat” operation, in which the current loop disturbances die out in one

switching cycle. Theoretically a current mode loop is stable with half the “dead-beat” slope (twice the calculated

slope capacitor value in Equation 25). A smaller slope capacitor results in larger slope signal which is better for

noise immunity in the transition region (VIN~VOUT). A larger slope signal, however, restricts the achievable input

voltage range for a given output voltage, switching frequency, and inductor. For this design CSLOPE = 100 pF is

selected for better transition region behavior while still providing the required VIN range. This selection of slope

capacitor, inductor, switching frequency, and inductor satisfies the COMP range limitation explained in Gm Error

Amplifier section.

9.2.2.9 UVLO

The UVLO resistor divider must be designed for turn-on below 6V. Selecting a RUV2 = 249 kΩ gives a UVLO

hysteresis of 0.8 V. The lower UVLO resistor is the selected using Equation 26:

(26)

A standard value of 59.0 kΩ is selected for RUV1.

When programming the UVLO threshold for lower input voltage operation, it is important to choose MOSFETs

with gate (Miller) plateau voltage lower than the minimum VIN.

9.2.2.10 Soft-Start Capacitor

The soft-start time is programmed using the soft-start capacitor. The relationship between CSS and the soft-start

time is given by:

(27)

CSS = 0.1 µF gives a soft-start time of 16 ms.

9.2.2.11 Dither Capacitor

The dither capacitor sets the modulation frequency of the frequency dithering around the nominal switching

frequency. A larger CDITH results in lower modulation frequency. For proper operation the modulation frequency

(FMOD) must be much lower than the switching frequency. Use Equation 28 to select CDITH for the target

modulation frequency.

(28)

For the current design dithering is not being implemented. Therefore a 0

Ω resistor from the DITH pin to AGND

disables this feature.