Note

After an undervoltage condition is cleared and the supplies have returned to valid levels, the device

typically resumes normal operation in 300 µs.

8.3.3.4 Floating Pins

The ISO1044B has internal pull-ups on critical pins which places the device into known states if the pin floats.

This internal bias should not be relied upon by design though, especially in noisy environments, but instead

should be considered a failsafe protection feature.

When a CAN controller supporting open drain outputs is used, an adequate external pull-up resistor must be

used to ensure that the TXD output of the CAN controller maintains adequate bit timing to the input of the CAN

transceiver.

8.3.3.5 Unpowered Device

The device is designed to be ideal passive or no load to the CAN bus if it is unpowered. The bus pins (CANH,

CANL) have extremely low leakage currents when the device is unpowered to avoid loading down the bus which

is critical if some nodes of the network are unpowered while the rest of the of network remains in operation.

8.3.3.6 CAN Bus Short Circuit Current Limiting

The device has two protection features that limit the short circuit current when a CAN bus line has a short-circuit

fault condition. The first protection feature is driver current limiting (both dominant and recessive states) and the

second feature is TXD dominant state time out to prevent permanent higher short circuit current of the dominant

state during a system fault. During CAN communication the bus switches between dominant and recessive

states, therefore the short circuit current may be viewed either as the instantaneous current during each bus

state or as an average current of the two states. For system current (power supply) and power considerations in

the termination resistors and common-mode choke ratings, use the average short circuit current. Determine the

ratio of dominant and recessive bits by the data in the CAN frame plus the following factors of the protocol and

PHY that force either recessive or dominant at certain times:

• Control fields with set bits

• Bit stuffing

• Interframe space

• TXD dominant time out (fault case limiting)

These factors ensure a minimum recessive amount of time on the bus even if the data field contains a high

percentage of dominant bits. The short circuit current of the bus depends on the ratio of recessive to dominant

bits and their respective short circuit currents. Use Equation 2 to calculate the average short circuit current.

IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive ×

IOS(SS)_REC]

(2)

where

• IOS(AVG) is the average short circuit current

• %Transmit is the percentage the node is transmitting CAN messages

• %Receive is the percentage the node is receiving CAN messages

• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages

• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages

• IOS(SS)_REC is the recessive steady state short circuit current

• IOS(SS)_DOM is the dominant steady state short circuit current

Note

Consider the short circuit current and possible fault cases of the network when sizing the power

ratings of the termination resistance and other network components.

www.ti.com

ISO1044

SLLSFB0A – MARCH 2020 – REVISED JULY 2020

Copyright © 2020 Texas Instruments Incorporated

Submit Document Feedback

21

Product Folder Links: ISO1044