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L9963E датащи(PDF) 55 Page - STMicroelectronics |
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L9963E датащи(HTML) 55 Page - STMicroelectronics |
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55 / 184 page ![]() For all regulators the slew rate at the power up can be evaluated considering corresponding current limitation applied on capacitance connected to related pin. The equation below estimates the startup time considering a 20% tolerance on the external stabilization capacitance (refer to Table 73). The VREG regulator implements a soft start strategy and its startup time is TVREG_SOFT_START. TVCOMstart=VVCOM×CVCOM IVCOM_curr_lim= 85−275 μs TVTREFstart=VVTREF×CVTREF IVTREF_curr_lim = 85−270 μs TVANAstart=VVANA×CVANA IVANA_curr_lim= 65−260 μs (5) Figure 18. Regular scheme 4.8.2 Bootstrap In order to provide a supply higher than VBAT to the level shifters of the ADC, a Bootstrap solution has been implemented. The Bootstrap is automatically enabled in NORMAL mode. The bootstrap works with an external capacitance CCB. Bootstrap works in 2 phases: • during phase 1 capacitance CCB is charged between 0 V and VREG for a time long TRELOAD_PHASE. • during phase 2 the same capacitance is bootstrapped, connecting its negative terminal to VBAT. This phase longs TBOOT_PHASE. A VREG OV condition turns off bootstrap circuit. L9963E Device regulators DS13636 - Rev 12 page 55/184 |
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