L9959 datasheet(30/49 Pages) STMICROELECTRONICS

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Application information

L9959

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DocID027540 Rev 3

4.5

/ABE pin

/ABE (Ability/Enable) is a bidirectional pin, with an open-drain output. In normal operating

condition, this pin is pulled up by an external resistor. If /ABE is set to low, the outputs enter

tristate mode.

/ABE can be used to switch off the outputs quickly by an external signal. It is possible to

connect the /ABE pins of several devices together, so all of them can be disabled in case

one detects an error, which is flagged by the /ABE pin.

4.6

VDD-monitor

VDD is monitored for under- and over-voltage referenced to GNDABE.

If VDD goes below VDD_THL or above VDD_THH, /ABE is pulled to low and the outputs enter

tristate mode after the time tFIL_OFF. The VDD-monitoring state is stored into the status and

control register (STACON_REG).

If VDD increases above VDD_THL, /ABE is pulled to high after the filter time tFIL_ON. The SPI

remains functional as long as VDD is above the power-on reset threshold.

The behavior of the pin /ABE and the output stages after VDD goes below VDD_THH from

VDD-over-voltage is determined by bit CONFIG 0 in the status and configuration register

(STATCON):

CONFIG0 = 1: /ABE is latched and the outputs remain in tristate

CONFIG0 = 0: /ABE goes to inactive and the output stages are enabled after the filtering

time tFIL_ON.

4.7

VDD-monitor test

VDD-Monitor blocks can be tested in the application via SPI. During this test, the output

stages are still switched off in case of over- and under-voltage.

Upper threshold

The over-voltage threshold can be reduced using the configuration registers 1 and 2

(CONFIG1 and CONFIG2) in the status and control register (STACON_REG) to VTEST_THH

(see Table 35: Status and configuration register (STATCON_REG)). Since VTEST_THH is

below the normal VDD voltage, the status bit STATUS0 shows a VDD over-voltage.

Lower threshold

The under-voltage threshold can be increased to VTEST_THL using CONFIG1 and CONFIG2

in the STATCON register. Since the VDD voltage is below VTEST_THL, the resulting VDD-

undervoltage resets STATUS0.

After leaving the VDD-monitor test mode, the bits in the STACON register return to their

normal state.

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