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CDCLVD1213

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SCAS897A – JULY 2010 – REVISED OCTOBER 2016

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Typical Application (continued)

9.2.1 Design Requirements

The CDCLVD1213 shown in Figure 15 is configured with a 156.25-MHz LVDS clock from the backplane as its

input frequency. The LVDS clock is AC-coupled. A resistor divider (and a 0.1-µF capacitor to reduce noise) is

used to set the bias voltage correctly at the VT pin. The configuration example is driving 4 LVDS receivers in a

line card application with the following properties:

•

The PHY device is capable of DC-coupling with an LVDS driver such as the CDCLVD1213. This PHY device

features internal termination so no additional components are required for proper operation.

•

The ASIC LVDS receiver features internal termination and operates at the same common-mode voltage as

the CDCLVD1213. Again, no additional components are required.

•

The FPGA requires external AC-coupling, but has internal termination. 0.1-µF capacitors are placed to

provide AC-coupling.

•

The CPU on output QD is internally terminated, and requires only external AC-coupling capacitors. The DIV

pin is pulled to ground with a 100-Ω resistor to set the frequency divider to 1 so that the CPU clock frequency

is also 156.25 MHz.

9.2.2 Detailed Design Procedure

See Input Termination for proper input terminations, dependent on single-ended or differential inputs.

See LVDS Output Termination for output termination schemes depending on the receiver application.

Unused outputs can be left floating.

In this example, the PHY, ASIC, and FPGA or CPU require different schemes. Power supply filtering and

bypassing is critical for low-noise applications.

See Power Supply Recommendations for recommended filtering techniques. A reference layout is provided in

Low-Additive Jitter, Four-LVDS-Outputs Clock Buffer With Divider EVM (SCAU044).

9.2.3 Application Curves

The CDCLVD12xx's low additive noise is shown in this line card application. The low noise 156.25-MHz source

with 67-fs RMS jitter drives the CDCLVD12xx, resulting in 80-fs RMS when integrated from 12 kHz to 20 MHz.

The resultant additive jitter is a low 44-fs RMS for this configuration.

Reference signal is low-noise Rohde and Schwarz SMA100A

Figure 16. CDCLVD12xx Reference Phase Noise,

67-fs RMS (12 kHz to 20 MHz)

Figure 17. CDCLVD12xx Output Phase Noise,

80-fs RMS (12 kHz to 20 MHz)