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CDCLVD1213 датащи(PDF) 6 Page - Texas Instruments

номер детали CDCLVD1213
подробное описание детали  CDCLVD1213 1:4 Low Additive Jitter LVDS Buffer With Divider
PDF  25 Pages
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производитель  TI2 [Texas Instruments]
домашняя страница  https://www.ti.com
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CDCLVD1213 датащи(HTML) 6 Page - Texas Instruments

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Frequency − MHz
700
T = 25 C
A
o
2.625V
2.5V
2.375V
6
CDCLVD1213
SCAS897A – JULY 2010 – REVISED OCTOBER 2016
www.ti.com
Product Folder Links: CDCLVD1213
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
6.7 Typical Characteristics
Input clock RMS jitter is 32 fs from 10 kHz to 20 MHz and additive
RMS jitter is 152 fs, TA = 25°C, and VCC = 2.5 V
Figure 1. 100-MHz Input and Output Phase Noise Plot
Figure 2. Differential Output Voltage vs Frequency



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