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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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L9026 датащи(PDF) 40 Page - STMicroelectronics |
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L9026 датащи(HTML) 40 Page - STMicroelectronics |
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40 / 60 page  11.2 Daisy chain capability L9026 implements SPI with daisy chain capability where a single master can address multiple slaves by driving a single NCS and MOSI lines, getting back data from a single MISO line as reported in the Figure 20. Figure 20. SPI Daisy chain configuration In order to gain flexibility, the daisy chain approach can be used not only to address multiple L9026 but the IC allows addressing also mixed configurations, provided that all the elements of the chain work with CPOL = 0, CPHA = 0. As reported in Figure 21, the only condition to be met is that the frame loaded inside each device of the chain is consistent and error free once the MNCS is de-asserted. Figure 21. SPI message in daisy chain configuration 11.3 SPI electrical specifications 3 V ≤ VDDIO ≤ 5.5 V; 6 V ≤ VBATT ≤ 18 V; -40 °C ≤ Tj ≤ 150 °C unless otherwise noticed. All voltages are referred to GND pin. Table 19. SPI electrical parameters Parameter Description Test condition Min Typ Max Unit Input SPI pins – low level VNCS(L) NCS - - - 0.8 V VCLK(L) CLK - - - 0.8 V VSI(L) SI - - - 0.8 V Input SPI pins – high level VNCS(H) NCS - 2 - - V VCLK(H) CLK - 2 - - V VSI(H) SI - 2 - - V Input pull up resistor at NCS pin RNCS L-input pull-up resistor at NCS pin VNCS = 0.8 V 40 58 95 KΩ L9026 SPI DS13397 - Rev 9 page 40/60 |
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