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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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L5965 датащи(PDF) 29 Page - STMicroelectronics |
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L5965 датащи(HTML) 29 Page - STMicroelectronics |
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29 / 73 page  4.2.14 Under-Voltage, Over-Voltage and Power-Good All regulators are monitored and Power-Good, Over-Voltage and Under-Voltage information is provided through SPI. One SPI bit allows to select between two threshold options: • UV/PG/OV of 91%, 95%, 108% • UV/PG/OV of 86%, 90%, 113% Over-voltage and Power-Good are checked when the signal is rising, the Under-Voltage is valid when the signal is falling. The next figure shows the relationships among these monitors. Figure 18. Output voltage and monitors V V V V V V V V V V V V OV PG GADG0407181523PS PG with Hysteresis UV with Hysteresis OV with Hysteresis Under-Voltage Power-Good Over-Voltage TYP PG min PG typ+ hyst PG max VOUT (100%) OV min OV typ + hyst OV max UV min UV typ + hyst UV max UV min UV typ UV max UV th Vth th th V V V PG min PG typ PG max th Vth th th th th th th th th th V V V OV min OV typ OV max th th th th th th th 4.2.15 Temperature control and VBATx voltage through internal ADC In order to provide an advanced on-chip temperature control, power outputs are grouped in 7 clusters with dedicated thermal sensors. The sensors are suitably located on the device. TH1 is associated to the internal VREF, TH2 to Buck1, TH3 to Buck2, TH4 to Buck3, TH5 to Buck4 and the Boost, TH6 to the LDO, TH7 to the center of the die. In case the temperature of a cluster reaches the thermal shutdown threshold, the event is written in the register, the fault pin is activated, and the single regulator is switched off (all other outputs remain active). In particular, what is described below takes place. Thermal Cluster TH1: in case the temperature of TH1 reaches the thermal shutdown threshold, the device moves to REC mode. The corresponding SPI bit is set and the FAULT pin is asserted. Thermal Clusters TH2, TH3, TH4, TH5, TH6: in case the temperature reaches the thermal shutdown threshold, the corresponding regulator, is shut down. The power stage is switched OFF with a 16 μs filter time. The output decreases and, when the UV is detected, the buck goes in REC state and can be restarted only when the OT flag is reset. The corresponding SPI bit is set and the FAULT pin is asserted. In case the thermal shutdown condition is suspended before the UV is detected, the regulator output turns on again. When the regulator is disabled by OTP, in case the temperature of that cluster reaches the thermal shutdown threshold, the corresponding SPI bit is set and the FAULT pin is asserted. Thermal Cluster TH7: in case the temperature of TH7 reaches the thermal shutdown threshold, the corresponding SPI bit is set and the FAULT pin is asserted. L5965 Voltage regulators and features description DS12567 - Rev 3 page 29/73 |
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