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STA369BW датащи(PDF) 40 Page - STMicroelectronics |
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STA369BW датащи(HTML) 40 Page - STMicroelectronics |
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40 / 89 page ![]() Register description STA369BW 40/89 DocID022033 Rev 2 8.3 Configuration register C (addr 0x02) 8.3.1 FFX power output mode The FFX power output mode selects how the FFX output timing is configured. Different power devices use different output modes. 8.3.2 FFX compensating pulse size register Table 6: D7 D6 D5 D4 D3 D2 D1 D0 OCRB CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0 1 0 11 111 Table 23. FFX power output mode Bit R/W RST Name Description 0R/W 1 OM0 Selects configuration of FFX output 1R/W 1 OM1 Table 24. Output modes OM[1,0] Output stage mode 00 Drop compensation 01 Discrete output stage - tapered compensation 10 Full power mode 11 Variable drop compensation (CSZx bits) Table 25. FFX compensating pulse size bits Bit R/W RST Name Description 2R/W 1 CSZ0 When OM[1,0] = 11, this register determines the size of the FFX compensating pulse from 0 clock ticks to 15 clock ticks. 3R/W 1 CSZ1 4R/W 1 CSZ2 5R/W 0 CSZ3 Table 26. Compensating pulse size CSZ[3:0] Compensating pulse size 0000 0 ns (0 tick) compensating pulse size 0001 20 ns (1 tick) clock period compensating pulse size …… 1111 300 ns (15 tick) clock period compensating pulse size |
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