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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STA369BW датащи(PDF) 51 Page - STMicroelectronics |
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STA369BW датащи(HTML) 51 Page - STMicroelectronics |
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51 / 89 page  DocID022033 Rev 2 51/89 STA369BW Register description 89 8.6.2 Invalid input detect mute enable Setting the IDE bit enables this function, which looks at the input I2S data and automatically mutes if the signals are perceived as invalid. 8.6.3 Binary output mode clock loss detection The BCLE bit detects loss of input MCLK in binary mode and will output 50% duty cycle. 8.6.4 LRCK double trigger protection The LDTE bit actively prevents double triggering of the LRCLK. 8.6.5 Auto EAPD on clock loss When active, the ECLE bit issues a power-stage device power-down signal (EAPD) on clock loss detection. 8.6.6 IC power-down The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted Table 46. Invalid input detect mute enable Bit R/W RST Name Description 2 R/W 1 IDE Setting of 1 enables the automatic invalid input detect mute Table 47. Binary output mode clock loss detection Bit R/W RST Name Description 3 R/W 1 BCLE Binary output mode clock loss detection enable Table 48. LRCK double trigger protection Bit R/W RST Name Description 4 R/W 1 LDTE LRCLK double trigger protection enable Table 49. Auto EAPD on clock loss Bit R/W RST Name Description 5 R/W 0 ECLE Auto EAPD on clock loss Table 50. IC power-down Bit R/W RST Name Description 7R/W 1 PWDN 0: IC power-down low-power condition 1: IC normal operation |
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