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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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L9678P датащи(PDF) 38 Page - STMicroelectronics |
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L9678P датащи(HTML) 38 Page - STMicroelectronics |
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38 / 215 page  Start-up power control L9678P, L9678P-S 38/216 DS11626 Rev 9 Figure 18. Internal voltage errors An active low pin output (RESET pin) is driven from the L9678P to allow resetting of external devices such as the microcontroller, sensors, and other ICs within the ECU. Three internal reset signals are generated by the device: POR Power On Reset - This reset is asserted when a failure is detected in the internal supplies or bandgap circuits. When active, all other resets are asserted. WSM_RESET Watchdog State Machine Reset - This reset is generated when the POR is active. SSM_RESET System State Machine Reset - This reset is asserted when the POR or the WSM_RESET are active, or when a failure is detected in either Watchdog state machine. The RESET pin is the active-low signal driven on the output pin, and is an inverted form of SSM_RESET. The cause of a RESET activation is latched and reported into the Fault Status Register FLTSR and cleared on SPI reading. During the RESET event the logic is under reset but the FLTSR is not reset. So the fault info will be available as soon as the IC will be out of reset. The reset logic shall be controlled as shown in the diagram below: GAPGPS01122 VINT3V3 VINT_OV VINT3V3 Monitor VINT_UV VDD_OV VDD Monitor VDD_UV VDD VREG_ERR VDD3V3_OV VDD3V3_ERR VDD3V3_UV VDD3V3 Monitor VDD3V3 VDD5_OV VDD5_ERR VDD5_UV VDD5 Monitor VDD5 VBGM (Monitor) GNDA Monitor GNDA GNDD GNDSUBx GNDD Monitor GNDA_ERR GNDD_ERR GND_ERR VBG_READY Reference for Controlling all supplies VBGR (Reference) |
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