VND9012AJ datasheet(45/46 Pages) STMICROELECTRONICS

45 / 46 page

List of figures

Figure 1.

Block diagram .................................................................... 3

Figure 2.

Configuration diagram (top view)........................................................ 4

Figure 3.

Current and voltage conventions........................................................ 5

Figure 4.

Switching time and Pulse skew ........................................................ 14

Figure 5.

Current sense timings (current sense mode)............................................... 14

Figure 6.

TDSTKON ....................................................................... 15

Figure 7.

Latch-off mode - Intermittent short circuit ................................................. 17

Figure 8.

Auto-restart mode - Intermittent short circuit ............................................... 18

Figure 9.

Auto-restart mode - Permanent short circuit ............................................... 19

Figure 10.

Standby mode activation ............................................................ 19

Figure 11.

Standby state diagram.............................................................. 20

Figure 12.

OFF-state output current ............................................................ 21

Figure 13.

Standby current .................................................................. 21

Figure 14.

IGND(ON) vs. Iout .................................................................. 21

Figure 15.

Logic Input high level voltage ......................................................... 21

Figure 16.

Logic Input low level voltage.......................................................... 21

Figure 17.

High level logic input current.......................................................... 21

Figure 18.

Low level logic input current .......................................................... 22

Figure 19.

Logic Input hysteresis voltage......................................................... 22

Figure 20.

FaultRST Input clamp voltage......................................................... 22

Figure 21.

Undervoltage shutdown ............................................................. 22

Figure 22.

On-state resistance vs. Tcase ......................................................... 22

Figure 23.

On-state resistance vs. VCC ......................................................... 22

Figure 24.

Turn-on voltage slope .............................................................. 23

Figure 25.

Turn-off voltage slope .............................................................. 23

Figure 26.

Won vs. Tcase ................................................................... 23

Figure 27.

Woff vs. Tcase ................................................................... 23

Figure 28.

ILIMH vs. Tcase ................................................................... 23

Figure 29.

OFF-state open-load voltage detection threshold ........................................... 23

Figure 30.

Vsense clamp vs. Tcase ............................................................. 24

Figure 31.

Vsenseh vs. Tcase ................................................................. 24

Figure 32.

Application diagram................................................................ 26

Figure 33.

Simplified internal structure .......................................................... 26

Figure 34.

M0-9 application schematic .......................................................... 28

Figure 35.

CurrentSense and diagnostic – block diagram ............................................. 29

Figure 36.

CurrentSense block diagram ......................................................... 29

Figure 37.

Analog HSD – open-load detection in off-state ............................................. 31

Figure 38.

Open-load / short to VCC condition ..................................................... 31

Figure 39.

Maximum turn off current versus inductance............................................... 33

Figure 40.

Maximum turn off energy versus inductance ............................................... 33

Figure 41.

PowerSSO-16 on two-layer PCB (2s0p to JEDEC JESD 51-5) .................................. 34

Figure 42.

PowerSSO-16 on four-layer PCB (2s2p to JEDEC JESD 51-7) .................................. 34

Figure 43.

Rthj-amb vs PCB copper area in open box free air condition (one channel on) ........................ 35

Figure 44.

PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) .................... 35

Figure 45.

Thermal fitting model of a double-channel HSD in PowerSSO-16 ................................ 36

Figure 46.

PowerSSO-16 package dimensions .................................................... 37

Figure 47.

PowerSSO-16 reel 13" ............................................................. 39

Figure 48.

PowerSSO-16 carrier tape ........................................................... 39

Figure 49.

PowerSSO-16 schematic drawing of leader and trailer tape .................................... 40

Figure 50.

PowerSSO-16 marking information ..................................................... 41

VND9012AJ

List of figures

DS12727 - Rev 5

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