STAMP0TR datasheet(3/62 Pages) STMICROELECTRONICS

3 / 62 page

STAMP0

Contents

DocID028639 Rev 1

3/62

4.8

Clock manager ................................................................................ 28

4.8.1

PLL ................................................................................................... 28

4.8.2

Oscillator........................................................................................... 30

4.8.3

PLL autoconf .................................................................................... 30

4.8.4

Low-clock check ............................................................................... 30

4.8.5

PLL_OSC_SEL................................................................................. 30

4.8.6

SYNC clock generator ...................................................................... 30

4.8.7

MIC clock out generator ................................................................... 31

4.8.8

PLL and oscillator power-down ........................................................ 31

I²C registers ................................................................................... 32

5.1

5.2

5.2.1

Soft-reset configuration (reg. 0x00).................................................. 34

5.2.2

PLL input division factor (IDF) and others (reg. 0x01) ..................... 34

5.2.3

PLL multiplication factor (integral part) named as N division factor

(NDIV) and dithering (reg. 0x02) ...................................................................... 35

5.2.4

PLL multiplication factor, fractional part MSB (reg. 0x03) ................ 36

5.2.5

PLL multiplication factor, fractional part LSB (reg. 0x04) ................. 36

5.2.6

Clock manager configuration register (reg.0x05) ............................. 36

5.2.7

Clock manager status register (reg. 0x06) ....................................... 36

5.2.8

Synchronization clock out configuration register (reg. 0x07) ........... 37

5.2.9

Clock manager configuration register (reg. 0x08) ............................ 38

5.2.10

TDM configuration register (reg. 0x09)............................................. 38

5.2.11

Channel 1 and 2 mapping configuration register (reg. 0x0A)........... 39

5.2.12

Channel 3 and 4 mapping configuration register (reg. 0x0B)........... 40

5.2.13

Channel 5 and 6 mapping configuration register (reg. 0x0C) .......... 40

5.2.14

Channel 7 and 8 mapping configuration register (reg. 0x0D) .......... 40

5.2.15

RMS meter threshold programming (reg. 0x0E) .............................. 40

5.2.16

RMS meter threshold value MSB (reg. 0x0F) .................................. 41

5.2.17

RMS meter threshold value LSB (reg. 0x10) ................................... 41

5.2.18

RMS meter enable value MSB (reg. 0x11)....................................... 41

5.2.19

RMS meter enable value LSB (reg.0x12)......................................... 41

5.2.20

RMS channel1 value MSB (reg.0x13) .............................................. 41

5.2.21

RMS channel1 value LSB (reg. 0x14) .............................................. 41

5.2.22

RMS channel2 value MSB (reg. 0x15) ............................................. 41

5.2.23

RMS channel2 value LSB (reg. 0x16) .............................................. 42

5.2.24

RMS channel3 value MSB (reg. 0x17) ............................................. 42

5.2.25

RMS channel3 value LSB (reg. 0x18) .............................................. 42

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