• The I2C clock and data pins have integrated high-voltage ESD protection circuits; however, adding a Zener

diode and series resistor provides more robust ESD performance. The I2C clock and data lines have an

internal pull-down. When the gas gauge senses that both lines are low (such as during removal of the pack),

the device performs auto-offset calibration and then goes into SLEEP mode to conserve power.

11.2 Layout Example

4

5

6

7

8

11

12

PACK +

PACK–

PBI

VC2

VC1

SRN

SRP

VSS

TS1

SCL

SDA

PACK

3

2

1

9

10

CHG

DSG

Fuse

1 s

2 s

PWPD

13

SCL

SDA

S

S

S

G

D D

D

D

S

S

S

G

D

D

D D

CSD16412Q5A

CSD16412Q5A

Via connects to Power Ground

Via connects between two layers

Differential Input well

matched for accuracy

Power Ground Trace

Power Trace Line

Thermistor

Reverse Polarity

Portection

Input filters

Bus

Communication

Exposed Thermal Pad

Figure 11-2. BQ28Z610-R1 Board Layout

BQ28Z610-R1

SLUSE07B – JANUARY 2020 – REVISED JANUARY 2022

www.ti.com

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