AMC7836IPAP datasheet(10/91 Pages) TI2

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AMC7836

SLAS986D – NOVEMBER 2014 – REVISED FEBRUARY 2018

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Electrical Characteristics: DAC (continued)

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These

specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of

the product containing it. AVDD = DVDD = 4.7 to 5.5 V, AVCC = 12 V, IOVDD = 1.8 to 5.5 V, AGND = DGND = 0 V, AVEE =

AVSSB = AVSSC = AVSSD = –12 V (for DAC groups in negative range) or 0 V (for DAC groups in positive ranges), DAC output

range = 0 to 10 V for all groups, no load on the DACs, TA = –40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(2)

The output voltage of each DAC group must not be greater than that of the corresponding AVCC pin (AVCC_AB or AVCC_CD) or lower than

that of the corresponding AVSS pin (AVEE, AVSSB, AVSSC or AVSSD). See the DAC Output Range and Clamp Configuration section for

more details.

(3)

If all channels are simultaneously loaded, care must be taken to ensure the thermal conditions for the device are not exceeded.

(4)

To be sampled during initial release to ensure compliance; not subject to production testing.

(5)

No DAC load to the DAC group AVSS pin.

DAC OUTPUT CHARACTERISTICS

Full-scale output voltage range(2)

Set at power-up or reset through auto-range

detection. The output range can be modified after

power-up or reset through the DAC range registers

(address 0x1E through 0x1F). DAC-RANGE = 100b

–10

The output range can be modified after power-up or

reset through the DAC range registers (address 0x1E

through 0x1F). DAC-RANGE = 101b

–5

Set at power-up or reset through auto-range

detection. The output range can be modified after

power-up or reset through the DAC range registers

(address 0x1E through 0x1F). DAC-RANGE = 111b

The output range can be modified after power-up or

reset through the DAC range registers (address 0x1E

through 0x1F). DAC-RANGE = 110b

Output voltage settling time

Transition: Code 400h to C00h to within ½ LSB, RL =

2 kΩ, CL = 200 pF. 0 to 10 V and –10 to 0 V ranges

µs

Transition: Code 400h to C00h to within ½ LSB, RL =

2 kΩ, CL = 200 pF. 0 to 5 V and –5 to 0 V ranges

Slew rate

Transition: Code 400h to C00h, 10% to 90%, RL = 2

kΩ, CL = 200 pF. 0 to 10 V and –10 to 0 V ranges

1.25

V/µs

Transition: Code 400h to C00h, 10% to 90%, RL = 2

kΩ, CL = 200 pF. 0 to 5 V and –5 to 0 V ranges

1.25

Short circuit current

Full-scale current shorted to the DAC group AVSS or

AVCC voltage

±45

Load current(3)

Source or sink with 1-V headroom from the DAC

group AVCC or AVSS voltage, voltage drop < 25 mV

±15

Source or sink with 300-mV headroom from the DAC

group AVCC or AVSS voltage, voltage drop < 25 mV

±10

Maximum capacitive load(4)

RL = ∞

DC output impedance

Code set to 800h, ±15mA

Power-on overshoot

AVEE = AVSSB = AVSSC = AVSSD = AGND, AVCC = 0

to 12 V, 2-ms ramp

Glitch energy

Transition: Code 7FFh to 800h; 800h to 7FFh

nV-s

Output noise

TA = 25°C, 1 kHz, code 800h, includes internal

reference noise

520

nV/

√Hz

TA = 25°C, integrated noise from 0.1 Hz to 10 Hz,

code 800h, includes internal reference noise

µVPP

CLAMP OUTPUTS

Clamp output voltage(5)

DAC output range: 0 to 10 V, AVSS = AGND

DAC output range: 0 to 5 V, AVSS = AGND

DAC output range: –10 to 0 V, AVSS = –12 V

AVSS + 2

DAC output range: –5 to 0 V, AVSS = –6 V

AVSS + 1

Clamp output impedance

kΩ

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