ADV7182ABCPZ datasheet(25/102 Pages) AD

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Data Sheet

ADV7182A

Rev. 0 | Page 25 of 102

Figure 13. Lock Related Signal Path

SRLS, Select Raw Lock Signal—Address 0x51, Bit 6

Using the SRLS bit, the user can choose between two sources for

determining the lock status per Bits[1:0] in the Status 1 register

(see Figure 13):



The TIME_WIN signal is based on a line to line evaluation

of the horizontal synchronization pulse of the incoming

video and reacts quickly.



The FREE_RUN signal evaluates the properties of the

incoming video over several fields, taking vertical

synchronization information into account.

Setting SRLS to 0 (default) selects the FREE_RUN signal; that

is, the signal evaluates the properties of the incoming video over

several fields.

Setting SRLS to 1 selects the TIME_WIN signal; that is, the

signal evaluates the horizontal synchronization pulse of the

incoming video on a line to line basis.

FSCLE, fSC Lock Enable—Address 0x51, Bit 7

The FSCLE bit allows the user to choose whether the status of

the color subcarrier loop is taken into account when the overall

lock status is determined and presented via Bits[1:0] in the

Status 1 register. This bit must be set to 0 when operating the

ADV7182A in YPrPb component mode to generate a reliable

HLOCK status bit.

When FSCLE is 0 (default), the overall lock status is dependent

only on horizontal sync lock. When FSCLE is 1, the overall lock

status is dependent on horizontal sync lock and fSC lock.

CIL[2:0], Count in to Lock—Address 0x51, Bits[2:0]

CIL[2:0] determines the number of consecutive lines for which

the lock condition must be true before the system switches into

the locked state and reports this via Bits[1:0] in the Status 1 register.

The bit counts the value in lines of video.

Table 23. CIL Function

CIL[2:0]

Number of Video Lines

000

001

010

011

100 (default)

100

101

500

110

1000

111

100,000

COL[2:0], Count Out of Lock (COL)—Address 0x51,

Bits[5:3]

COL[2:0] determines the number of consecutive lines for which

the out of lock condition must be true before the system switches

into the unlocked state and reports this via Bits[1:0] in the

Status 1 register. COL[2:0] counts the value in lines of video.

Table 24. COL Function

COL[2:0]

Number of Video Lines

000

001

010

011

100 (default)

100

101

500

110

1000

111

100,000

COLOR CONTROL REGISTERS

The color control registers allow the user to control picture

appearance, including control of active data in the event of

video being lost. These controls are independent of any other

controls. For instance, brightness control is independent of

picture clamping, although both controls affect the dc level of

the signal.

CON[7:0], Contrast Adjust—Address 0x08, Bits[7:0]

This register allows the user to control contrast adjustment of

the picture.

Table 25. CON Function

CON[7:0]

Description

0x80 (default)

Gain on luma channel = 1

0x00

Gain on luma channel = 0

0xFF

Gain on luma channel = 2

TIME_WIN

FREE_RUN

STATUS 1[0]

SELECT THE RAW LOCK SIGNAL

SRLS

FILTER THE RAW LOCK SIGNAL

CIL[2:0], COL[2:0]

TAKE fSC LOCK INTO ACCOUNT

FSCLE

STATUS 1[1]

fSC LOCK

COUNTER INTO LOCK

COUNTER OUT OF LOCK

MEMORY

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