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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADV7182ABCPZ датащи(PDF) 17 Page - Analog Devices |
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ADV7182ABCPZ датащи(HTML) 17 Page - Analog Devices |
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17 / 102 page  Data Sheet ADV7182A Rev. 0 | Page 17 of 102 ANTIALIASING FILTERS The ADV7182A has optional on-chip antialiasing (AA) filters on each of the four channels that are multiplexed to the ADC (see Figure 9). The filters are designed for standard definition video up to 10 MHz bandwidth. Figure 10 and Figure 11 show the filter magnitude and phase characteristics. The antialiasing filters are enabled by default and the selection of INSEL[4:0] determines which filters are powered up at any given time. For example, if CVBS mode is selected, the filter circuits for the remaining input channels are powered down to conserve power. However, the antialiasing filters can be disabled or bypassed using the AA_FILT_MAN_OVR control. Figure 9. Antialias Filter Configuration Figure 10. Antialiasing Filter Magnitude Response Figure 11. Antialiasing Filter Phase Response AA_FILT_MAN_OVR, Antialiasing Filter Override— Address 0xF3, Bit 4 This feature allows the user to override the antialiasing filters on/off settings, which are automatically selected by INSEL[4:0]. AA_FILT_EN[3:0], Antialiasing Filter Enable— Address 0xF3, Bits[3:0] These bits allow the user to enable or disable the antialiasing filters on each of the four input channels multiplexed to the ADC. When disabled, the analog signal bypasses the AA filters and is routed directly to the ADC. AA_FILT_EN[0], Antialiasing Filter Enable—Address 0xF3, Bit 0 When AA_FILT_EN[0] is 0, AA Filter 1 is disabled. When AA_FILT_EN[0] is 1, AA Filter 1 is enabled. AA_FILT_EN[1], Antialiasing Filter Enable—Address 0xF3, Bit 1 When AA_FILT_EN[1] is 0, AA Filter 2 is disabled. When AA_FILT_EN[1] is 1, AA Filter 2 is enabled. AA_FILT_EN[2], Antialiasing Filter Enable—Address 0xF3, Bit 2 When AA_FILT_EN[2] is 0, AA Filter 3 is disabled. When AA_FILT_EN[2] is 1, AA Filter 3 is enabled. AA_FILT_EN[3], Antialiasing Filter Enable—Address 0xF3, Bit 3 When AA_FILT_EN[3] is 0, AA Filter 4 is disabled. When AA_FILT_EN[3] is 1, AA Filter 4 is enabled. Table 11. Manual Mux Settings for ADC (MAN_MUX_EN Must be Set to 1)1, 2, 3, 4 MUX_0[2:0] ADC Connected To MUX_1[2:0] ADC Connected To MUX_2[2:0] ADC Connected To MUX_3[2:0] ADC Connected To 000 No connect 000 No connect 000 No connect 000 No connect 001 AIN1 001 No connect 001 No connect 001 No connect 010 AIN2 010 AIN2 010 AIN2 010 AIN2 011 AIN3 011 No connect 011 AIN3 011 No connect 100 AIN4 100 AIN4 100 No connect 100 AIN4 1 CVBS can only be processed by MUX_0. 2 Differential CVBS can only be processed by MUX_0 (positive channel) and MUX_3 (negative channel). 3 Y/C can only be processed by MUX_0 and MUX_1. 4 YPrPb can only be processed by MUX_0, MUX_1, and MUX_2. AIN1 AIN2 AIN3 AIN4 AA FILTER 1 AA FILTER 2 AA FILTER 3 AA FILTER 4 10-BIT, 86MHz ADC ADC SHA + – 0 –36 1k 100M FREQUENCY (Hz) 10k 100k 1M 10M –4 –8 –12 –16 –20 –24 –28 –32 0 –150 1k 100M FREQUENCY (Hz) 10k 100k 1M 10M –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 |
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