LP3470M5X-3.08

U2

VINA

VIND

LM2830

U3

U1

LM2830

SW

D1

FB

EN

L1

GND

C1

C2

R1

R2

C3

VINA

VIND

SW

FB

EN

GND

D2

L2

C4

R4

R5

R6

3

1

2

VIN

RESET

4

5

LP3470

C7

VIN

VO = 3.3V @ 1.0A

VO = 1.2V @ 1.0A

R3

LM2830, LM2830-Q1

SNVS454E – AUGUST 2006 – REVISED DECEMBER 2014

www.ti.com

8.2.6 LM2830X Dual Converters With Delayed Enabled Design

Figure 27 shows proposed solution with two LM2830 devices. Output of device on top (3.3-V output) is used to

control the enable pin of the lower device, thus ensuring that the second device (1.2-V output) can not turn on

before the output of first device (3.3-V in this example) reaches steady state. Additionally, small POR supervisory

(LP3470) circuit is used to monitor enable voltage for lower device. The RESET pin on POR circuit is open drain

and requires typically 20-k

Ω pullup resistor to the monitored voltage.

Figure 27. LM2830X (1.6 MHz): Vin = 5 V, Vo = 1.2 V at 1.0 A and 3.3 V at 1.0-A Schematic

Table 7. Bill of Materials

PART ID

PART VALUE

MANUFACTURER

PART NUMBER

U1, U2

1.0-A Buck Regulator

TI

LM2830X

U3

Power on Reset

TI

LP3470M5X-3.08

C1, C3 Input Cap

22 µF, 6.3 V, X5R

TDK

C3216X5ROJ226M

C2, C4 Output Cap

22 µF, 6.3 V, X5R

TDK

C3216X5ROJ226M

C7

Trr delay capacitor

TDK

D1, D2 Catch Diode

0.3 Vf Schottky 1.5 A, 30 VR

TOSHIBA

CRS08

L1, L2

3.3 µH, 1.3 A

Coilcraft

ME3220-332

R2, R4, R5

10.0 k

Ω, 1%

Vishay

CRCW08051002F

R1, R6

45.3 k

Ω, 1%

Vishay

CRCW08054532F

R3

100 k

Ω, 1%

Vishay

CRCW08051003F

22

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