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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7580 датащи(PDF) 15 Page - STMicroelectronics |
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ST7580 датащи(HTML) 15 Page - STMicroelectronics |
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15 / 33 page  DocID022644 Rev 2 15/33 ST7580 Analog front-end (AFE) 33 5 Analog front-end (AFE) 5.1 Reception path Figure 5 shows the block diagram of the ST7580 input receiving path. The main blocks are a wide input range analog programmable gain amplifier (PGA) and the analog to digital converter (ADC). Figure 5. Reception path block diagram The PGA is controlled by an embedded loop algorithm, adapting the PGA gain to amplify or attenuate the input signal according to the input voltage range for the ADC. The PGA gain ranges from -18 dB up to 30 dB, with steps of 6 dB (typ.), as described in Table 7. Table 7. PGA gain table PGA code PGA gain (typ.) [dB] RX_IN max. range [V p-p] 0 -18 V(RX_IN) MAX 1-12 8 2-6 4 30 2 46 1 5 12 0.500 6 18 0.250 7 24 0.125 830 0.0625 AM02505v1 RX AFE BPF ADC RX_IN BPF BPF ADC ADC PGA PGA |
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