6.6 Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)(1)

PARAMETER

TEST CONDITIONS(2)

MIN

TYP

MAX

UNIT

VOL

DC output low voltage

IOL = 2 mA

0.2 × VDD

V

CAPACITANCE

CIN

Input capacitance LPSDR

ƒ = 1 MHz

10

pF

Input capacitance SubLVDS

ƒ = 1 MHz

20

pF

COUT

Output capacitance

ƒ = 1 MHz

10

pF

CRESET

Reset group capacitance

ƒ = 1 MHz; (1080 × 240)

micromirrors

400

450

pF

(1)

Device electrical characteristics are over unless otherwise noted.

(2)

All voltage values are with respect to the ground pins (VSS).

(3)

To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.

(4)

Supply power dissipation based on non–compressed commands and data.

(5)

To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.

(6)

Supply power dissipation based on 3 global resets in 200 µs.

(7)

The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are

also required.

(8)

LPSDR specifications are for pins LS_CLK and LS_WDATA.

(9)

Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC

Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.

(10) LPSDR specification is for pin LS_RDATA.

6.7 Timing Requirements

Device electrical characteristics are over unless otherwise noted.

MIN

NOM

MAX

UNIT

LPSDR

tr

Rise slew rate(1)

(30% to 80%) × VDD, Figure 6-3

1

3

V/ns

tƒ

Fall slew rate(1)

(70% to 20%) × VDD, Figure 6-3

1

3

V/ns

tr

Rise slew rate(2)

(20% to 80%) × VDD, Figure 6-4

0.25

V/ns

tƒ

Fall slew rate(2)

(80% to 20%) × VDD, Figure 6-4

0.25

V/ns

tc

Cycle time LS_CLK,

Figure 6-2

7.7

8.3

ns

tW(H)

Pulse duration LS_CLK high

50% to 50% reference points, Figure

6-2

3.1

ns

tW(L)

Pulse duration LS_CLK low

50% to 50% reference points, Figure

6-2

3.1

ns

tsu

Setup time

LS_WDATA valid before LS_CLK ↑,

Figure 6-2

1.5

ns

t h

Hold time

LS_WDATA valid after LS_CLK ↑,

Figure 6-2

1.5

ns

tWINDOW

Window time(1) (3)

Setup time + Hold time, Figure 6-2

3.0

ns

tDERATING

Window time derating(1) (3)

For each 0.25 V/ns reduction in slew

rate below 1 V/ns, Figure 6-6

0.35

ns

SubLVDS

tr

Rise slew rate

20% to 80% reference points, Figure

6-5

0.7

1

V/ns

tƒ

Fall slew rate

80% to 20% reference points, Figure

6-5

0.7

1

V/ns

tc

Cycle time DCLK,

Figure 6-7

1.79

1.85

ns

tW(H)

Pulse duration DCLK high

50% to 50% reference points, Figure

6-7

0.79

ns

tW(L)

Pulse duration DCLK low

50% to 50% reference points, Figure

6-7

0.79

ns

www.ti.com

DLP4710LC

DLPS178C – MAY 2020 – REVISED JULY 2023

Copyright © 2023 Texas Instruments Incorporated

Submit Document Feedback

13

Product Folder Links: DLP4710LC