6 Detailed Description

6.1 Overview

The ’HC273 and ’HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with

silicon-gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits.

Information at the D input is transferred to the Q outputs on the positive-going edge of the clock pulse. All eight

flip-flops are controlled by a common clock (CLK) and a common reset (CLR). Resetting is accomplished by a

low voltage level independent of the clock. All eight Q outputs are reset to a logic 0.

6.2 Functional Block Diagram

D

R

Q

xD

xQ

One of Eight D-Type Flip-Flops

CLK

CLR

Shared Control Logic

6.3 Device Functional Modes

Table 6-1. Truth Table(1)

INPUTS

OUTPUT

RESET (CLR)

CLOCK CLK

DATA Dn

Q

L

X

X

L

H

↑

H

H

H

↑

L

L

H

L

X

Q0

(1)

H = high voltage level, L = low voltage level, X = don’t care, ↑ =

transition from low to high level, Q0 = level before the indicated

steady-state input conditions were established

CD54HC273, CD74HC273

CD54HCT273, CD74HCT273

SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022

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