CS

DOUT

DIN

tSU_CSCK

SCLK

ADD3

WRITE

REPEAT

AIN0

AIN1

AIN2

AIN3

EXT_REF

STANDBY

TMP_AVG

ADD2

6

ADD1

ADD0

DB11

DB10

DB2

DB1

DB0

tPH_CSZ

tCONV

tDV_CSDO

3-State

5

4

3

2

1

13

tPH_SCLK

tSCLK

tD_CKDO

tHT_CKDO

tHT_CKDI

tSU_CKDI

14

15

16

3-State

tPL_SCLK

tDZ_CKDO

t

ACQ

ADS8028

SBAS549B – MAY 2011 – REVISED MARCH 2012

www.ti.com

PARAMETER MEASUREMENT INFORMATION

TIMING CHARACTERISTICS

Figure 1. Serial Interface Timing Diagram

Timing Requirements for Figure 1(1)

ADS8028

PARAMETER

DESCRIPTION

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fSCLK

External serial clock frequency

20

MHz

tSCLK

External interface clock time period

50

ns

tPH_SCLK

SCLK high pulse width

0.4 tSCLK

0.6 tSCLK

ns

tPL_SCLK

SCLK low pulse width

0.4 tSCLK

0.6 tSCLK

ns

Conversion time:

tSU_CSCK + 13 tSCLK

ns

tCONV

For channels AIN0 to AIN7

fSCLK = 20 MHz

700

ns

For internal temperature sensor measurement

100

µs

tPH_CSZ

CS high pulse width

6

ns

tACQ

Acquisition time (for channel AINx)

fSCLK = 20 MHz

100

ns

tSU_CSCK

Setup time: CS to SCLK falling edge

10

ns

tDV_CSDO

Delay time between CS falling edge to DOUT enabled

17

ns

DVDD = 1.65 V to 3 V

32

ns

Delay time between SCLK falling edge to (new) data

tD_CKDO

DVDD = 3 V to 3.6 V

29

ns

available on DOUT

DVDD = 3.6 V to 5.25 V

28

ns

Hold time: SCLK falling edge to (previous) data valid on

tHT_CKDO

10

ns

DOUT

Delay time between 16th SCLK falling edge to DOUT

tDZ_CKDO

12

27

ns

going to high-impedance

Delay time between CS going high to DOUT going to high-

tDZ_CSDO

26

ns

impedance

tSU_CKDI

DIN setup time before SCLK falling edge

5

ns

tHT_CKDI

DIN hold time after SCLK falling edge

4

ns

tACQ_TMP

TM_BUSY falling edge to CS falling edge

100

ns

tPU_STANDBY

Power-up time after coming out of STANDBY mode

1

µs

Internal reference mode,

tPOWER_UP

Power-up time after coming out of power-down mode

6

ms

10-µF capacitor on REF pin

(1)

Specifications apply from TA = –40°C to +125°C, AVDD = 2.7 V to 3.6 V, DVDD = 1.65 V to 5.25 V, VREF = 2.5 V internal, load on

DOUT = 15 pF || 100 k

Ω, and tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 0.5 DVDD, unless otherwise

noted.

6

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