7 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

7.1 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the

Recommended Operating Conditions table.

Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single

supply, 0.1μf is recommended; if there are multiple VCC pins, then 0.01μf or 0.022 μf is recommended for each

power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1μf and

a 1μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as

possible for best results.

7.2 Layout

7.2.1 Layout Guidelines

When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions

of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are

used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because

the undefined voltages at the outside connections result in undefined operational states. Specified in Layout

Diagram are rules that must be observed under all circumstances. All unused inputs of digital logic devices

must be connected to a high or low bias to prevent them from floating. The logic level that should be applied

to any particular unused input depends on the function of the device. Generally they will be tied to GND or

VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is

a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when

asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.

7.2.2 Layout Example

1

2

3

4

5

6

7

16

15

14

13

12

11

10

GND

V

CC

0.1

F

Bypass capacitor

placed close to the

device

Avoid 90°

corners for

signal lines

Recommend GND flood fill for

improved signal isolation, noise

reduction, and thermal dissipation

Unused output

left floating

8

9

A/B

1A

1B

1Y

2A

2B

2Y

GND

V

CC

G

4A

4B

4Y

3A

3B

3Y

Unused inputs

tied to VCC

Figure 7-1. Example Layout for the CD74ACT157

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CD74ACT157

SCHS340C – MARCH 2003 – REVISED AUGUST 2024

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