RF430CL331HIPWR datasheet(46/63 Pages) TI2

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RF430CL331H

SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015

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5.11.11 Buffer Start Register

This register is written after a Read Binary command by the host controller indicating the index in buffer

memory where the data started to be written. On an Update Binary command, this register indicates

where the RF430CL331H has started to write the packet in its buffer memory.

Table 5-37. Buffer Start Register

ADDRESS

0xFFE5

Buffer Start MSB

ADDRESS

0xFFE4

Buffer Start LSB

Table 5-38. Buffer Start Register Description

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-8

Buffer Start MSB

R/W

Buffer start most significant byte.

7-0

Buffer Start LSB

R/W

Buffer start least significant byte.

5.11.12 SWTX Register

When a PCD issues a command, there is a time-out that is negotiated (FWI in the SENSB_RES/ATQB

command). The RF430CL331H has this amount of time to respond to the PCD command. If this time-out

cannot be met by RF430CL331H, the NFC protocol allows a sending a S(WTX) request (refer to Section

13.2.2 of the NFC Digital Protocol). This allows the time-out to be restarted after the PCD S(WTX)

response.

When the internal state machine determines that a wait time extension is necessary, it uses this register

value to populate the INF field of the S(WTX) request (refer to Table 84 of the NFC Digital Protocol). This

custom setting response allows flexibility in negotiating this wait time extension.

Table 5-39. SWTX Register

ADDRESS

0xFFDF

Reserved

ADDRESS

0xFFDE

SWTX Request

Table 5-40. SWTX Register Description

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-8

Reserved

R/W

Reserved for future use. Write with 0.

7-0

SWTX Request

R/W

S(WTX) request byte.

Detailed Description

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