RF430CL331HIPWR datasheet(28/63 Pages) TI2

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RF430CL331H

SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015

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4. Dynamic Tag RF430CL331H procedure:

(a) Only the requested data (even if extra was supplied) is included in the response packet to the

PCD. The status words are appended to the response packet per NFC Type 4 specification.

(b) If the command was valid, the status words are SW1 = 90h and SW2 = 00h.

Status Word Response register.

(d) RF transmission starts, the Extra Data interrupt is always asserted.

5. The host controller must service the Extra Data interrupt by appending to the buffer extra sequential

data up until the buffer size (3000 bytes).

(a) Checks the source of the interrupt by reading the interrupt registers.

(b) The interrupt is an Extra Data interrupt.

storing the data.

NOTE

When the Extra Data interrupt is enabled, the interrupt always occurs when the

RF430CL331H is responding to the Read Binary request. However, this does not mean

that every interrupt service can add to the RF430CL331H buffer (3000 bytes). If the

Buffer Start register read indicates its index is at the end of the buffer, then no more data

can be added. In this case the NDEF Block Length register should be set to 0 indicating

that no data was added to the buffer. On the next Read Binary request, the valid data in

the RF430CL331H buffer is shifted to the beginning to allow more room for extra data to

be appended again.

(d) NDEF File Offset register can be read.

(e) Write sequential extra data to the buffer starting at the Buffer Start register index.

(f) The time limit of writing extra data to the buffer is until the next Read Binary command is

completed to be transmitted to the RF430CL331H. After that point, latency starts to be introduced

into the system as the processing of the new packet is delayed.

(g) Update the NDEF Block Length register with how many bytes were written into the buffer. If none,

set to 0.

(h) The prefetch interrupt must be cleared by writing to the Interrupt Flag register.

(i) Set the Extra Data Send In bit in the Host Response register.

(j) This completes servicing of the Read Prefetch interrupt.

Detailed Description

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