LP8552 datasheet(35/49 Pages) TI2

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LP8552

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SNVS693E – SEPTEMBER 2011 – REVISED SEPTEMBER 2014

8.6.2.8 EEPROM Address 7

Address A7h

EEPROM ADDRESS 7 REGISTER

PLL[4:0]

EN_F_RES

HYSTERESIS[1:0]

Name

Bit

Access

Description

PLL

7:3

R/W

13-bit counter value for PLL, 5 LSB bits. PLL[12:0] bits are used when en_vsync = 1. See

Table 8 below for PLL value calculation.

EN_F_RES

R/W

Enable PWM output frequency set resistor

0 = Resistor is disabled and PWM output frequency is set with PWM_FREQ EEPROM

1 = PWM frequency set resistor is enabled. RFSET defines the output PWM frequency. See

table in PWM Frequency Setting for full description of the PWM frequencies.

HYSTERESIS

1:0

R/W

PWM input hysteresis function. Will define how small changes in the PWM input are

ignored to remove constant switching between two values.

00 = OFF

01 = 1-bit hysteresis with 11-bit resolution

10 = 1-bit hysteresis with 10-bit resolution

11 = 1-bit hysteresis with 8-bit resolution

Table 8. PLL Value Calculation

en_vsync

PLL FREQUENCY [MHz]

PLL[12:0]

5, 10, 20, 40

not used

5 MHz / (26 x fVSYNC)

10 MHz / (50 x fVSYNC)

20 MHz / (98 x fVSYNC)

40 MHz / (196 x fVSYNC)

PLL frequency is set by PWM_RESOLUTION[1:0] bits.

For example:

If fPLL = 5 MHz and fVSYNC = 60 Hz, then PLL[12:0] = 5000000 Hz / (26 * 60 Hz) = 3205d = C85h.

If fPLL = 10 MHz and fVSYNC = 75 Hz, then PLL[12:0] = 10000000 Hz / (50 * 75 Hz) = 2667d = A6Bh.

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