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DP83849IFVS/NOPB датащи(PDF) 60 Page - Texas Instruments |
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DP83849IFVS/NOPB датащи(HTML) 60 Page - Texas Instruments |
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60 / 108 page ![]() 50: 50: 130: 130: 0.1 PF 0.1 PF Vdd 130: 130: 130: All values are typical abd are +/- 1% PLACE RESISTORS AND CAPACITORS CLOSE TO THE DEVICE PLACE RESISTORS CLOSE TO THE FIBER TRANSCEIVER FXTDP FXTDM FXSD FXRDP FXRDM 80: 80: 80: 80: 80: TD+ TD- SD RD+ RD- DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com 8.2 FIBER NETWORK CIRCUIT Figure 8-2 shows the recommended circuit for a 100 Mb/s fiber pair interface. Figure 8-2. 100 Mb/s Fiber Pair Interface 8.3 ESD PROTECTION Typically, ESD precautions are predominantly in effect when handling the devices or board before being installed in a system. In those cases, strict handling procedures need be implemented during the manufacturing process to greatly reduce the occurrences of catastrophic ESD events. After the system is assembled, internal components are less sensitive from ESD events. The network interface pins are more susceptible to ESD events. 60 Design Guidelines Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83849IF |
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