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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DP83849IFVS/NOPB датащи(PDF) 28 Page - Texas Instruments |
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DP83849IFVS/NOPB датащи(HTML) 28 Page - Texas Instruments |
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28 / 108 page  Data IDLE Data (J/K) (TR) T2.27.4 T2.27.1 T2.27.5 T2.27.3 T2.27.2 T2.27.2 T2.27.2 T2.27.2 PMD Input Pair X1 RX_DV CRS_DV RXD[1:0] RX_ER DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com 4.31 AC Specifications — RMII Receive Timing (1) (2) (3) (4) Parameter Description Notes Min Typ Max Units T2.27.1 X1 Clock Period 50 MHz Reference Clock 20 ns T2.27.2 RXD[1:0], CRS_DV, RX_DV and 2 14 ns RX_ER output delay from X1 rising T2.27.3 CRS ON delay (100Mb)(5) 100BASE-TX mode 18.5 bits 100BASE-FX mode 9 T2.27.4 CRS OFF delay (100Mb) 100BASE-TX mode 27 bits 100BASE-FX mode 17 T2.27.5 RXD[1:0] and RX_ER latency 100BASE-TX mode 38 bits (100Mb) 100BASE-FX mode 27 (1) Per the RMII Specification, output delays assume a 25pF load. (2) CRS_DV is asserted asynchronously in order to minimize latency of control signals through the Phy. CRS_DV may toggle synchronously at the end of the packet to indicate CRS deassertion. (3) RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of receive data. (4) Receive Latency is measured from the first bit of the symbol pair on the PMD Receive Pair. Typical values are with the Elasticity Buffer set to the default value (01). (5) CRS ON delay is measured from the first bit of the JK symbol on the PMD Receive Pair to initial assertion of CRS_DV. 28 Electrical Specifications Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83849IF |
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